公开(公告)号：US20250142975A1

公开(公告)日：2025-05-01

申请号：US18915623

申请日：2024-10-15

Applicant: Renesas Electronics Corporation

Inventor： Yasuyuki MORISHITA ,  Koki NARITA ,  Satoshi MAEDA

IPC: H01L27/02 ,  H02H9/04

Abstract: A semiconductor device includes a semiconductor chip having a plurality of layers formed on a surface. Here, a power supply wiring to which a power supply voltage is supplied, a ground wiring to which a ground voltage is supplied, MOS transistors connected to the power supply and ground wirings, and a trigger circuit, which is electrically connected to a gate electrode of the MOS transistor via a first wiring, are formed in the plurality of layers. The MOS transistors and the trigger circuit are formed in a first layer, the first wiring is formed in a second layer which is an upper layer of the first layer, and the first wiring includes a first portion extending in a first direction and a second portion which extends in a second direction intersecting the first direction and is electrically connected to the first portion.

公开(公告)号：US20180040609A1

公开(公告)日：2018-02-08

申请号：US15553138

申请日：2015-06-19

Applicant: Renesas Electronics Corporation

Inventor： Satoshi MAEDA ,  Yasuyuki MORISHITA ,  Masanori TANAKA

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/50

Abstract: A semiconductor device provided with: a first input/output circuit connected to a first pad; a second input/output circuit disposed in the direction along one side constituted by a chip edge in relation to the first input/output circuit, the second input/output circuit being connected to a second pad; and an ESD protective circuit disposed near the outer-side chip edge of the first and second input/output circuits. The ESD protection circuit is provided with a resistor, a capacitor, an inverter, and an N-channel-type transistor.

公开(公告)号：US20230092555A1

公开(公告)日：2023-03-23

申请号：US17945357

申请日：2022-09-15

Applicant: Renesas Electronics Corporation.

Inventor： Yasuyuki MORISHITA

IPC: H01L27/02

Abstract: A semiconductor device includes a protection element configured by a MOSFET, and the protection element has a multilayer metal wiring structure. The multilayer metal wiring structure includes drain connection wirings connected to drain regions of the MOSFET and source connection wirings connected to source regions of the MOSFET. In a part of a layer of the multilayer metal wiring structure where both the drain connection wirings and the source connection wirings are present, only either the drain connection wirings or the source connection wirings are laid out in a grained pattern.

公开(公告)号：US20220020739A1

公开(公告)日：2022-01-20

申请号：US17349547

申请日：2021-06-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuyuki MORISHITA

IPC: H01L27/02 ,  H03K17/687

Abstract: A first ESD protection circuit is provided between a first high-potential side power supply and a first low-potential side power supply of a first power supply system and a second ESD protection circuit is provided between a second high-potential side power supply and a second low-potential side power supply of a second power supply system. A coupling circuit includes a bidirectional diode and couples the first and second low-potential side power supplies. A first transistor is composed of an n-channel MOS transistor, has a drain coupled to the first high-potential side power supply of the first power supply system, and has a back gate coupled to the second low-potential side power supply of the second power supply system. A resistor element is inserted in series between the drain of the first transistor and the first high-potential side power supply.

公开(公告)号：US20180211949A1

公开(公告)日：2018-07-26

申请号：US15858242

申请日：2017-12-29

Applicant: Renesas Electronics Corporation

Inventor： Yoshihito UZAWA ,  Yasuyuki MORISHITA ,  Masanori TANAKA

IPC: H01L27/02 ,  H01L27/06

CPC classification number: H01L27/027 ,  H01L27/0255 ,  H01L27/0277 ,  H01L27/0288 ,  H01L27/0629

Abstract: A semiconductor device includes a MOS transistor which is coupled between two terminals and discharges current which flows caused by generation of static electricity and a diode which is coupled between a back gate of the MOS transistor and one of the terminal and has a polarity which is reversed to the polarity of a parasitic diode which is formed between the back gate and a source of the MOS transistor.

公开(公告)号：US20130228824A1

公开(公告)日：2013-09-05

申请号：US13781263

申请日：2013-02-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuyuki MORISHITA

IPC: H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/74 ,  H01L29/7436

Abstract: An electrostatic protection circuit in a semiconductor device includes a first first-conductivity type well extending in a first direction over a semiconductor substrate, a second first-conductivity type well extending in a second direction over the semiconductor substrate and perpendicular to the first direction with one end coupled to a first long side of the first first-conductivity type well, and a second-conductivity type well formed around the first first-conductivity type well and the second first-conductivity type well. It also includes a first high-concentration second-conductivity type region extending in the second direction on a surface of the second first-conductivity type well and a first high-concentration first-conductivity type region extending in the second direction on a surface of the second-conductivity type well while facing the first high-concentration second-conductivity type region.

Abstract translation: 半导体器件中的静电保护电路包括在半导体衬底上沿第一方向延伸的第一第一导电型阱，在半导体衬底上沿第二方向延伸并垂直于第一方向的第二第一导电型阱，其中一个 端部耦合到第一第一导电类型阱的第一长边，以及围绕第一第一导电类型阱和第二第一导电类型阱形成的第二导电类型阱。 它还包括在第二第一导电类型阱的表面上沿第二方向延伸的第一高浓度第二导电类型区域和在第二导电类型阱的表面上沿第二方向延伸的第一高浓度第一导电类型区域 第二导电型阱同时面向第一高浓度第二导电类型区域。

公开(公告)号：US20250022871A1

公开(公告)日：2025-01-16

申请号：US18767265

申请日：2024-07-09

Applicant: Renesas Electronics Corporation

Inventor： Yasuyuki MORISHITA

IPC: H01L27/02

Abstract: A semiconductor device is provided. The semiconductor device includes an input/output cell, a core logic circuit, a first power supply cell, a second power supply cell, a third power supply cell and a fourth power supply cell. Each of the power supply cells includes a protection circuit and a bidirectional diode.

公开(公告)号：US20230139094A1

公开(公告)日：2023-05-04

申请号：US17964267

申请日：2022-10-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuyuki MORISHITA

IPC: H01L27/02

Abstract: A semiconductor device includes an input/output cell, an IO power supply cell, a core power supply cell, and a core logic circuit arranged on a chip, and the core power supply cell includes an ESD protection circuit. The input/output cell includes a level shifter circuit and the level shifter circuit is arranged in the input/output cell. The core logic circuit is arranged outside the input/output cell. The core power supply cell is not arranged in the same row as the input/output cell, but is arranged in a third region provided between a first region in which the input/output cell and the IO power supply cell are arranged and a second region in which the core logic circuit is arranged.

公开(公告)号：US20170331284A1

公开(公告)日：2017-11-16

申请号：US15469450

申请日：2017-03-24

Applicant: Renesas Electronics Corporation

Inventor： Yasuyuki MORISHITA

IPC: H02H9/04 ,  H01L27/02

Abstract: A semiconductor device that can have both noise resistance and ESD resistance is provided.The semiconductor device includes a first and a second digital circuits, a first and a second ground potential lines respectively provided corresponding to the first and the second digital circuits, a first and a second analog circuits, a third and a fourth ground potential lines respectively provided corresponding to the first and the second analog circuits, a first bidirectional diode group provided between the first and the second ground potential lines, a second bidirectional diode group provided between the third and the fourth ground potential lines, and a third bidirectional diode group provided between the first and the third ground potential lines. The number of stages of bidirectional diodes of the third bidirectional diode group is greater than that included in each of the first and the second bidirectional diode groups.