公开(公告)号：US20180052784A1

公开(公告)日：2018-02-22

申请号：US15796321

申请日：2017-10-27

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro OMURA ,  Ryohei YOSHIDA ,  Takanobu NARUSE ,  Seiichi SAITO

IPC: G06F13/16 ,  G06F12/0813

CPC classification number: G06F13/1663 ,  G06F12/0813

Abstract: A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.

公开(公告)号：US20130073765A1

公开(公告)日：2013-03-21

申请号：US13674043

申请日：2012-11-11

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiko HOTTA ,  Seiichi SAITO ,  Hiroyuki HAMASAKI ,  Hirotaka HARA ,  Itaru NONOMURA

IPC: G06F13/24

CPC classification number: G06F1/3253 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D10/151

Abstract: In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.

Abstract translation: 在具有总线控制器的数据处理器中，总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，提供定时控制电路 在外围电路和总线控制器之间，并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器 速度时钟信号，使定时控制电路响应于指向外围电路的写指令而启动，与高速时钟信号的周期同步地写入外围电路，并且与 低速时钟信号的周期。