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    SEMICONDUCTOR DEVICE AND MEMORY ACCESS CONTROL METHOD
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND MEMORY ACCESS CONTROL METHOD 审中-公开

    公开(公告)号：US20170255509A1

    公开(公告)日：2017-09-07

    申请号：US15446501

    申请日：2017-03-01

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yukitoshi TSUBOI ,  Hiroyuki HAMASAKI

    IPC: G06F11/10

    CPC classification number: G06F11/1016 ,  G06F11/1044

    Abstract: The detection of a fault of the address signal system in memory access is aimed at. A semiconductor device according to the present invention includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

    SEMICONDUCTOR DEVICE AND IMAGE PROCESSING METHOD
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND IMAGE PROCESSING METHOD 有权
    半导体器件和图像处理方法

    公开(公告)号：US20170034471A1

    公开(公告)日：2017-02-02

    申请号：US15290831

    申请日：2016-10-11

    Applicant: Renesas Electronics Corporation

    Inventor： Hiroyuki HAMASAKI ,  Atsushi NAKAMURA ,  Manabu KOIKE ,  Hideaki KIDO ,  Nobuyasu KANEKAWA

    IPC: H04N5/77 ,  G06T1/20 ,  H04N5/265 ,  H04N5/91 ,  H04N5/232 ,  G06T1/60

    CPC classification number: H04N5/77 ,  G06T1/20 ,  G06T1/60 ,  G06T2200/28 ,  H04N5/23229 ,  H04N5/265 ,  H04N5/91

    Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

    Abstract translation: 图像处理装置包括图像处理单元，其从一个图像数据计算两种图像数据并输出计算出的图像数据;数据组合单元，其组合从图像处理单元提供的两种数据，并将该组合数据输出到 一个终端，输出缓冲器，根据从用于仲裁总线的总线仲裁装置提供的指令调整组合数据的输出定时;以及数据分配单元，其以从形式输出从输出缓冲器输出到总线的组合数据 或者分发组合数据，并根据外部组合分配指令将分布式数据输出到总线。

    SEMICONDUCTOR DEVICE AND MEMORY ACCESS CONTROL METHOD
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND MEMORY ACCESS CONTROL METHOD 审中-公开

    公开(公告)号：US20190317854A1

    公开(公告)日：2019-10-17

    申请号：US16451915

    申请日：2019-06-25

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yukitoshi TSUBOI ,  Hiroyuki HAMASAKI

    IPC: G06F11/10

    Abstract: A semiconductor device includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

    SEMICONDUCTOR DEVICE AND FAILURE DETECTION METHOD OF THE SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND FAILURE DETECTION METHOD OF THE SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190163655A1

    公开(公告)日：2019-05-30

    申请号：US16151161

    申请日：2018-10-03

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kyohei YAMAGUCHI ,  Daisuke KAWAKAMI ,  Hiroyuki HAMASAKI

    IPC: G06F13/24

    Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

    INTERRUPT MONITORING SYSTEMS AND METHODS FOR FAILURE DETECTION FOR A SEMICONDUCTOR DEVICE
    6.
    发明申请
    INTERRUPT MONITORING SYSTEMS AND METHODS FOR FAILURE DETECTION FOR A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210263869A1

    公开(公告)日：2021-08-26

    申请号：US17319799

    申请日：2021-05-13

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kyohei YAMAGUCHI ,  Daisuke KAWAKAMI ,  Hiroyuki HAMASAKI

    IPC: G06F13/24 ,  G06F11/07

    Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

    SEMICONDUCTOR DEVICE AND DATA PROCESSOR
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND DATA PROCESSOR 有权
    半导体器件和数据处理器

    公开(公告)号：US20130073765A1

    公开(公告)日：2013-03-21

    申请号：US13674043

    申请日：2012-11-11

    Applicant: Renesas Electronics Corporation

    Inventor： Yoshihiko HOTTA ,  Seiichi SAITO ,  Hiroyuki HAMASAKI ,  Hirotaka HARA ,  Itaru NONOMURA

    IPC: G06F13/24

    CPC classification number: G06F1/3253 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D10/151

    Abstract: In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.

    Abstract translation: 在具有总线控制器的数据处理器中，总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，提供定时控制电路 在外围电路和总线控制器之间，并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器 速度时钟信号，使定时控制电路响应于指向外围电路的写指令而启动，与高速时钟信号的周期同步地写入外围电路，并且与 低速时钟信号的周期。

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