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公开(公告)号：US09281291B2
公开(公告)日：2016-03-08
申请号：US14589539
申请日：2015-01-05
发明人： Masami Koketsu , Toshiaki Sawada
IPC分类号： H01L21/78 , H01L21/46 , H01L23/00 , H01L23/544 , H01L23/58 , H01L29/78 , H01L23/535 , H01L27/12
CPC分类号： H01L23/544 , H01L23/5226 , H01L23/5283 , H01L23/535 , H01L23/585 , H01L24/13 , H01L24/29 , H01L24/81 , H01L24/83 , H01L27/124 , H01L27/1248 , H01L29/78 , H01L2223/5442 , H01L2223/54426 , H01L2223/5448 , H01L2224/16 , H01L2224/8113 , H01L2224/8185 , H01L2224/83101 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01054 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/04941 , H01L2924/0781 , H01L2924/12042 , H01L2924/1306 , H01L2924/14 , H01L2924/1426 , H01L2924/1433 , H01L2924/15788 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要： To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.
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公开(公告)号：US10056336B2
公开(公告)日：2018-08-21
申请号：US15709733
申请日：2017-09-20
发明人： Masami Koketsu , Toshiaki Sawada
IPC分类号： H01L23/544 , H01L23/58 , H01L23/00 , H01L23/528 , H01L23/522 , H01L27/12 , H01L23/535 , H01L29/78
CPC分类号： H01L23/544 , H01L23/5226 , H01L23/5283 , H01L23/535 , H01L23/585 , H01L24/13 , H01L24/29 , H01L24/81 , H01L24/83 , H01L27/124 , H01L27/1248 , H01L29/78 , H01L2223/5442 , H01L2223/54426 , H01L2223/5448 , H01L2224/16 , H01L2224/8113 , H01L2224/8185 , H01L2224/83101 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01054 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/04941 , H01L2924/0781 , H01L2924/12042 , H01L2924/1306 , H01L2924/14 , H01L2924/1426 , H01L2924/1433 , H01L2924/15788 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要： To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.
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公开(公告)号：US09799609B2
公开(公告)日：2017-10-24
申请号：US15290205
申请日：2016-10-11
发明人： Masami Koketsu , Toshiaki Sawada
IPC分类号： H01L23/544 , H01L23/58 , H01L23/00 , H01L29/78 , H01L23/535 , H01L27/12 , H01L23/522 , H01L23/528
CPC分类号： H01L23/544 , H01L23/5226 , H01L23/5283 , H01L23/535 , H01L23/585 , H01L24/13 , H01L24/29 , H01L24/81 , H01L24/83 , H01L27/124 , H01L27/1248 , H01L29/78 , H01L2223/5442 , H01L2223/54426 , H01L2223/5448 , H01L2224/16 , H01L2224/8113 , H01L2224/8185 , H01L2224/83101 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01054 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/04941 , H01L2924/0781 , H01L2924/12042 , H01L2924/1306 , H01L2924/14 , H01L2924/1426 , H01L2924/1433 , H01L2924/15788 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要： To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.
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公开(公告)号：US08633603B2
公开(公告)日：2014-01-21
申请号：US13840625
申请日：2013-03-15
发明人： Masami Koketsu , Toshiaki Sawada
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L23/5226 , H01L23/5283 , H01L23/535 , H01L23/585 , H01L24/13 , H01L24/29 , H01L24/81 , H01L24/83 , H01L27/124 , H01L27/1248 , H01L29/78 , H01L2223/5442 , H01L2223/54426 , H01L2223/5448 , H01L2224/16 , H01L2224/8113 , H01L2224/8185 , H01L2224/83101 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01054 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/04941 , H01L2924/0781 , H01L2924/12042 , H01L2924/1306 , H01L2924/14 , H01L2924/1426 , H01L2924/1433 , H01L2924/15788 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要： In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern Pib is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.
摘要翻译： 在构成LCD驱动器的半导体芯片中，在半导体衬底上的对准标记形成区域中形成标记。 标记形成在与集成电路形成区域中的最上层布线（第三层布线）相同的层中。 然后，在标记的下层和标记周围的背景区域形成图案。 此时，图案P1a形成在与第二层布线相同的层中，并且图案Pib形成在与第一层布线相同的层中。 此外，图案P2形成在与栅极电极相同的层中，并且图案P3形成在与元件隔离区域相同的层中。
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公开(公告)号：US09536839B2
公开(公告)日：2017-01-03
申请号：US14941829
申请日：2015-11-16
发明人： Masami Koketsu , Toshiaki Sawada
IPC分类号： H01L23/544 , H01L23/58 , H01L23/00 , H01L29/78 , H01L23/535 , H01L27/12 , H01L23/522 , H01L23/528
CPC分类号： H01L23/544 , H01L23/5226 , H01L23/5283 , H01L23/535 , H01L23/585 , H01L24/13 , H01L24/29 , H01L24/81 , H01L24/83 , H01L27/124 , H01L27/1248 , H01L29/78 , H01L2223/5442 , H01L2223/54426 , H01L2223/5448 , H01L2224/16 , H01L2224/8113 , H01L2224/8185 , H01L2224/83101 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01054 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/04941 , H01L2924/0781 , H01L2924/12042 , H01L2924/1306 , H01L2924/14 , H01L2924/1426 , H01L2924/1433 , H01L2924/15788 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要： To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.
摘要翻译： 通过提高对准标记的可视性，提供能够高精度地定位半导体芯片和安装基板的技术。 在构成LCD驱动器的半导体芯片中，在半导体衬底上的对准标记形成区域中形成标记。 标记形成在与集成电路形成区域中的最上层布线（第三层布线）相同的层中。 然后，在标记的下层和标记周围的背景区域形成图案。 此时，图案P1a形成在与第二层布线相同的层中，并且图案P1b形成在与第一层布线相同的层中。 此外，图案P2形成在与栅极电极相同的层中，并且图案P3形成在与元件隔离区域相同的层中。
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公开(公告)号：US08952555B2
公开(公告)日：2015-02-10
申请号：US14143207
申请日：2013-12-30
发明人： Masami Koketsu , Toshiaki Sawada
IPC分类号： H01L23/544 , H01L23/58 , H01L23/00 , H01L29/78 , H01L23/535
CPC分类号： H01L23/544 , H01L23/5226 , H01L23/5283 , H01L23/535 , H01L23/585 , H01L24/13 , H01L24/29 , H01L24/81 , H01L24/83 , H01L27/124 , H01L27/1248 , H01L29/78 , H01L2223/5442 , H01L2223/54426 , H01L2223/5448 , H01L2224/16 , H01L2224/8113 , H01L2224/8185 , H01L2224/83101 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01054 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/04941 , H01L2924/0781 , H01L2924/12042 , H01L2924/1306 , H01L2924/14 , H01L2924/1426 , H01L2924/1433 , H01L2924/15788 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要： To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.
摘要翻译： 通过提高对准标记的可视性，提供能够高精度地定位半导体芯片和安装基板的技术。 在构成LCD驱动器的半导体芯片中，在半导体衬底上的对准标记形成区域中形成标记。 标记形成在与集成电路形成区域中的最上层布线（第三层布线）相同的层中。 然后，在标记的下层和标记周围的背景区域形成图案。 此时，图案P1a形成在与第二层布线相同的层中，并且图案P1b形成在与第一层布线相同的层中。 此外，图案P2形成在与栅极电极相同的层中，并且图案P3形成在与元件隔离区域相同的层中。
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