公开(公告)号：US10056336B2

公开(公告)日：2018-08-21

申请号：US15709733

申请日：2017-09-20

Applicant: Renesas Electronics Corporation

Inventor： Masami Koketsu ,  Toshiaki Sawada

IPC: H01L23/544 ,  H01L23/58 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L27/12 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L23/544 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/585 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/8113 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01054 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/1433 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

公开(公告)号：US10002824B2

公开(公告)日：2018-06-19

申请号：US15619463

申请日：2017-06-10

Applicant: INTEL CORPORATION

Inventor： Ankur Agrawal ,  Srinivas S. Moola ,  Sujit Sharan ,  Vijay Govindarajan

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/02

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L23/02 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/544 ,  H01L23/564 ,  H01L24/16 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/10135 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2924/01028 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Incorporating at least one magnetic alignment structure on a microelectronic device and incorporating at least one alignment coil within a microelectronic substrate, wherein the alignment coil may be powered to form a magnetic field to attract the magnetic alignment structure, thereby aligning the microelectronic device to the microelectronic substrate. After alignment, the microelectronic device may be electrically attached to the substrate. Embodiments may include additionally incorporating an alignment detection coil within the microelectronic substrate, wherein the alignment detection coil may be powered to form a magnetic field to detect variations in the magnetic field generated by the alignment coil in order verify the alignment of the microelectronic device to the microelectronic substrate.

公开(公告)号：US20180114767A1

公开(公告)日：2018-04-26

申请号：US15789065

申请日：2017-10-20

Applicant: Kulicke and Soffa Industries, Inc.

Inventor： Matthew B. Wasserman

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L23/544 ,  H01L24/80 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/75305 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/8113 ,  H01L2224/81132

Abstract: A bond head assembly for a bonding machine is provided. The bond head assembly includes a body portion and a bonding tool for bonding a semiconductor element to a substrate. The bonding tool is secured to the body portion. The bond head assembly also includes at least one reflective optical element carried by the bond head assembly. The at least one reflective optical element is configured to be positioned along an optical path of the bonding machine such that a vision system of the bonding machine is configured to view a portion of the semiconductor element while being carried by the bonding tool prior to bonding of the semiconductor element to the substrate.

公开(公告)号：US09799609B2

公开(公告)日：2017-10-24

申请号：US15290205

申请日：2016-10-11

Applicant: Renesas Electronics Corporation

Inventor： Masami Koketsu ,  Toshiaki Sawada

IPC: H01L23/544 ,  H01L23/58 ,  H01L23/00 ,  H01L29/78 ,  H01L23/535 ,  H01L27/12 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/544 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/585 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/8113 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01054 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/1433 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

公开(公告)号：US09786580B2

公开(公告)日：2017-10-10

申请号：US14081969

申请日：2013-11-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Yang ,  Ming-Tsu Chung ,  Hong-Ye Shih ,  Jiung Wu ,  Chen-Yu Tsai ,  Hsin-Yu Chen ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L29/40 ,  H01L23/48 ,  H01L21/768 ,  H01L23/544 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/544 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03

Abstract: An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.

公开(公告)号：US20170278783A1

公开(公告)日：2017-09-28

申请号：US15619463

申请日：2017-06-10

Applicant: INTEL CORPORATION

Inventor： Ankur Agrawal ,  Srinivas S. Moola ,  Sujit Sharan ,  Vijay Govindarajan

IPC: H01L23/498 ,  H01L23/02 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L23/02 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/544 ,  H01L23/564 ,  H01L24/16 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/10135 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2924/01028 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Incorporating at least one magnetic alignment structure on a microelectronic device and incorporating at least one alignment coil within a microelectronic substrate, wherein the alignment coil may be powered to form a magnetic field to attract the magnetic alignment structure, thereby aligning the microelectronic device to the microelectronic substrate. After alignment, the microelectronic device may be electrically attached to the substrate. Embodiments may include additionally incorporating an alignment detection coil within the microelectronic substrate, wherein the alignment detection coil may be powered to form a magnetic field to detect variations in the magnetic field generated by the alignment coil in order verify the alignment of the microelectronic device to the microelectronic substrate.

公开(公告)号：US09570414B2

公开(公告)日：2017-02-14

申请号：US14474686

申请日：2014-09-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi Tsukiyama ,  Masatoshi Fukuda ,  Yukifumi Oyama ,  Shinya Fukayama

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/07 ,  H01L23/544 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L25/074 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/10135 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/1415 ,  H01L2224/14505 ,  H01L2224/16146 ,  H01L2224/1705 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81862 ,  H01L2224/81907 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/35 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2224/8185 ,  H01L2924/0665 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.

Abstract translation: 根据一个实施例，第一电极形成在第一半导体芯片的第一面上，第二电极和突起形成在第二半导体芯片的第二面上。 第一半导体芯片和第二半导体芯片通过突起彼此间隔开，使得第一面和第二面彼此面对。 第一半导体芯片和第二半导体芯片经受回流以彼此电连接，然后突起在低于回流温度的温度下固化。

公开(公告)号：US20170033052A1

公开(公告)日：2017-02-02

申请号：US15290205

申请日：2016-10-11

Applicant: Renesas Electronics Corporation

Inventor： Masami KOKETSU ,  Toshiaki SAWADA

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/535 ,  H01L23/58 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/544 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/585 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/8113 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01054 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/1433 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

Abstract translation: 通过提高对准标记的可视性，提供能够高精度地定位半导体芯片和安装基板的技术。 在构成LCD驱动器的半导体芯片中，在半导体衬底上的对准标记形成区域中形成标记。 标记形成在与集成电路形成区域中的最上层布线（第三层布线）相同的层中。 然后，在标记的下层和标记周围的背景区域形成图案。 此时，图案P1a形成在与第二层布线相同的层中，并且图案P1b形成在与第一层布线相同的层中。 此外，图案P2形成在与栅极电极相同的层中，并且图案P3形成在与元件隔离区域相同的层中。

公开(公告)号：US09548290B2

公开(公告)日：2017-01-17

申请号：US13487163

申请日：2012-06-02

Applicant: Satoru Wakiyama ,  Masaki Minami

Inventor： Satoru Wakiyama ,  Masaki Minami

IPC: H01L23/544 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L27/146

CPC classification number: H01L25/50 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L27/1464 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/08147 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/14131 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81011 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83862 ,  H01L2224/9221 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a semiconductor element, a connection electrode formed on the semiconductor element, and alignment marks formed on the semiconductor element. At least one of the alignment marks is made of a magnetic material.

Abstract translation: 半导体器件包括半导体元件，形成在半导体元件上的连接电极和形成在半导体元件上的对准标记。 对准标记中的至少一个由磁性材料制成。

公开(公告)号：US20170005068A1

公开(公告)日：2017-01-05

申请号：US15038963

申请日：2014-11-19

Applicant: TORAY ENGINEERING CO., LTD.

Inventor： Koji NISHIMURA ,  Katsumi TERADA ,  Mikio KAWAKAMI

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/75252 ,  H01L2224/75753 ,  H01L2224/75843 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/00014

Abstract: A three-dimensional mounting method for successively laminating N number of upper-layer joining materials includes positioning a first upper-layer joining material relative to a lowermost-layer joining material by recognizing an alignment position of the lowermost-layer joining material and a lower face alignment position of the first upper-layer joining material by a two-field image recognition unit, storing positional coordinates of the alignment position of the lowermost-layer joining material, positioning an (n+1)-th upper-layer joining material relative to an n-th upper-layer joining material by recognizing an upper face alignment position of the n-th upper-layer joining material and a lower face alignment position of the (n+1)-th upper-layer joining material, storing positional coordinates of the upper face alignment position of the n-th upper-layer joining material, recognizing an upper face alignment position of the N-th uppermost-layer joining material, and storing positional coordinates of the upper face alignment position of the N-th uppermost-layer joining material.

Abstract translation: 用于连续层压N个上层接合材料的三维安装方法包括通过识别最下层接合材料的对准位置和相对于最下层接合材料的下表面定位第一上层接合材料相对于最下层接合材料 通过双场图像识别单元对第一上层接合材料的对准位置，存储最下层接合材料的取向位置的位置坐标，定位第（n + 1）个上层接合材料相对于 通过识别第n个上层接合材料的上表面对准位置和第（n + 1）个上层接合材料的下表面对准位置，第n个上层接合材料，存储位置坐标 第n个上层接合材料的上表面对准位置，识别第N个最上层接合材料的上表面对准位置，并且存储位置 第N个最上层接合材料的上表面对准位置的坐标。