公开(公告)号：US20180082977A1

公开(公告)日：2018-03-22

申请号：US15640493

申请日：2017-07-01

申请人： Renesas Electronics Corporation

发明人： Yuki YAGYU

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L23/31

CPC分类号： H01L24/85 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/05647 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45687 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/7815 ,  H01L2224/78756 ,  H01L2224/8502 ,  H01L2224/85051 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/85355 ,  H01L2224/85359 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2224/85898 ,  H01L2224/85948 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2924/0541 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/0103 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01106 ,  H01L2924/01107 ,  H01L2224/45664 ,  H01L2924/00015

摘要： Reliability of a semiconductor device is improved.A wire bonding step includes a step of exposing a wire and a pad electrode to a reducing gas atmosphere, forming a first hydroxyl layer on a surface of a ball portion, and forming a second hydroxyl layer on a surface of the pad electrode, a first bonding step of temporarily joining the ball portion to the pad electrode through the first hydroxyl layer and the second hydroxyl layer, and after the first bonding step, a step of actually joining the ball portion to the pad electrode by performing a heat treatment on a semiconductor chip and a base material.

公开(公告)号：US09899583B2

公开(公告)日：2018-02-20

申请号：US15373220

申请日：2016-12-08

申请人： DAI NIPPON PRINTING CO., LTD.

发明人： Kazunori Oda ,  Masaki Yazaki

IPC分类号： H01L23/495 ,  H01L33/62 ,  F21V7/22 ,  F21V23/00 ,  H01L33/48 ,  F21V21/00 ,  H01L33/52 ,  H01L33/60 ,  H01L23/482 ,  H01L33/54 ,  H01L33/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  F21Y101/00 ,  F21Y115/10

CPC分类号： H01L33/62 ,  F21V7/22 ,  F21V21/00 ,  F21V23/005 ,  F21Y2101/00 ,  F21Y2115/10 ,  H01L23/3142 ,  H01L23/4824 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/49861 ,  H01L23/562 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L33/48 ,  H01L33/486 ,  H01L33/52 ,  H01L33/54 ,  H01L33/56 ,  H01L33/60 ,  H01L2224/05554 ,  H01L2224/16245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48639 ,  H01L2224/85439 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2933/0033 ,  H01L2933/005 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region.

公开(公告)号：US20170271227A1

公开(公告)日：2017-09-21

申请号：US15146893

申请日：2016-05-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sih-Hao Liao ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC分类号： H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

CPC分类号： H01L21/6835 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/32 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/12105 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/18162

摘要： An integrated fan-out package including a die, an insulating encapsulation, a filler, and a redistribution circuit structure is provided. The insulating encapsulation encapsulates sidewalls of the die, and the insulating encapsulation includes a recess on a top surface thereof. The filler covers the top surface of the insulating encapsulation and is being at least partially filled in the recess. The redistribution circuit structure covers an active surface of the die and the filler while being electrically connected to the die. The redistribution structure includes a dielectric layer covering the die and the filler. In addition, a method of manufacturing integrated fan-out packages is also provided.

公开(公告)号：US20170207149A1

公开(公告)日：2017-07-20

申请号：US15260069

申请日：2016-09-08

申请人： Dazhong LIANG

发明人： Dazhong LIANG

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/29 ,  H01L21/48

CPC分类号： H01L23/49541 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/293 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49586 ,  H01L23/562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45639 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01032 ,  H01L2924/01041 ,  H01L2924/0104 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention relates to the technical field of integrated circuit package, and more specifically, this invention relates to a high density integrated circuit package structure and an integrated circuit with this package structure. A high density integrated circuit package structure according to this invention comprises a sealed metal lead frame, a chip, and a cuboid plastic package structure with micron connecting wires. The length (A1) of the plastic package structure meets the relationship 1.20 mm+(B−8)×0.3 mm/2≦A1≦4.50 mm+(B−8)×1.00 mm/2, the width (A2) of the plastic package structure meets the relationship 1.20 mm≦A2≦3.50 mm, the thickness (A3) of the plastic package structure meets the relationship A3≧0.35 mm, and B is the number of the outer leads and is an integer number meeting the relationship 4≦B≦68. A package structure according to this invention may meet the demands generated when chip manufacturing technology progresses from micron scale to sub-micron scale, or even nanometer scale. It may satisfy the requirements of low power consumption, high speed, large capacity and small volume for portable products.

公开(公告)号：US09698115B2

公开(公告)日：2017-07-04

申请号：US15167904

申请日：2016-05-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Ming Chen ,  Cheng-Hsien Hsieh ,  Sung-Hui Huang ,  Kuo-Ching Hsu

IPC分类号： H01L23/00 ,  B23K1/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  B23K101/40

CPC分类号： H01L24/16 ,  B23K1/0016 ,  B23K2101/40 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13176 ,  H01L2224/16145 ,  H01L2224/16503 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/81

摘要： A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

公开(公告)号：US09659926B2

公开(公告)日：2017-05-23

申请号：US15200246

申请日：2016-07-01

申请人： Renesas Electronics Corporation

发明人： Shinya Suzuki ,  Kiichi Makuta

IPC分类号： H01L27/02 ,  G02F1/1345 ,  H01L23/00 ,  H01L23/498 ,  G02F1/133 ,  H01L23/532

CPC分类号： H01L24/17 ,  G02F1/13306 ,  G02F1/13452 ,  H01L23/49811 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0292 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13644 ,  H01L2224/1403 ,  H01L2224/1412 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/9211 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.

公开(公告)号：US09598772B2

公开(公告)日：2017-03-21

申请号：US12761863

申请日：2010-04-16

申请人： Chih-Wei Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chung-Shi Liu

发明人： Chih-Wei Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chung-Shi Liu

IPC分类号： H01L23/498 ,  H01L21/3205 ,  C23C18/16 ,  H01L23/00 ,  H01L23/31

CPC分类号： C23C18/1605 ,  C23C18/165 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2924/0002 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method for fabricating bump structure without UBM undercut uses an electroless Cu plating process to selectively form a Cu UBM layer on a Ti UBM layer within an opening of a photoresist layer. After stripping the photoresist layer, there is no need to perform a wet etching process on the Cu UBM layer, and thereby the UBM structure has a non-undercut profile.

公开(公告)号：US09597754B2

公开(公告)日：2017-03-21

申请号：US14000886

申请日：2012-02-15

申请人： Gaku Kanou

发明人： Gaku Kanou

IPC分类号： B23K35/30 ,  C22C9/00 ,  C25C1/12 ,  C22C9/08 ,  H01L23/00

CPC分类号： B23K35/302 ,  C22C9/00 ,  C22C9/08 ,  C25C1/12 ,  H01L24/43 ,  H01L24/45 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/01204 ,  H01L2924/01005 ,  H01L2924/01056 ,  H01L2924/01004 ,  H01L2924/01083 ,  H01L2924/0102 ,  H01L2924/01058 ,  H01L2924/01027 ,  H01L2924/01024 ,  H01L2924/01066 ,  H01L2924/01063 ,  H01L2924/01064 ,  H01L2924/01032 ,  H01L2924/01049 ,  H01L2924/01077 ,  H01L2924/01057 ,  H01L2924/01012 ,  H01L2924/01042 ,  H01L2924/0106 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01045 ,  H01L2924/01044 ,  H01L2924/01051 ,  H01L2924/0105 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01022 ,  H01L2924/0107 ,  H01L2924/0103 ,  H01L2924/0104 ,  H01L2924/01092 ,  H01L2924/20752 ,  H01L2924/013 ,  H01L2224/48

摘要： Copper or a copper alloy characterized in having an α-ray emission of 0.001 cph/cm2 or less. Since recent semiconductor devices are produced to have higher density and higher capacity, there is greater risk of soft errors caused by the influence of α rays emitted from materials positioned near semiconductor chips. In particular, there are strong demands for achieving higher purification of copper and copper alloys which are used near the semiconductor device, such as copper or copper alloy wiring lines, copper or copper alloy bonding wires, and soldering materials, and materials reduced in α-ray emission are also demanded. Thus, the present invention elucidates the phenomenon in which α rays are emitted from copper or copper alloys, and provides copper or copper alloy reduced in α-ray emission which is adaptable to the demanded material, and a bonding wire in which such copper or copper alloy is used as its raw material.

公开(公告)号：US20170062358A1

公开(公告)日：2017-03-02

申请号：US15232815

申请日：2016-08-10

申请人： Infineon Technologies AG

发明人： FRANK PUESCHNER ,  JENS POHL

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49855 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/50 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/1134 ,  H01L2224/11464 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1624 ,  H01L2224/16257 ,  H01L2224/1626 ,  H01L2224/26175 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/27618 ,  H01L2224/27622 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/29386 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/753 ,  H01L2224/7598 ,  H01L2224/81 ,  H01L2224/81903 ,  H01L2224/8314 ,  H01L2224/83203 ,  H01L2224/83208 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/01012 ,  H01L2924/0103 ,  H01L2924/0104 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2224/83

摘要： According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

摘要翻译： 根据各种实施例，芯片载体可以包括：配置成支撑芯片的芯片支撑区域; 芯片接触区域，包括用于电接触芯片的至少一个接触焊盘; 其中所述芯片载体在所述芯片接触区域中变薄，使得所述至少一个接触焊盘处的所述芯片载体的第一厚度小于所述芯片支撑区域中的所述芯片载体的第二厚度。

公开(公告)号：US09559069B2

公开(公告)日：2017-01-31

申请号：US14609023

申请日：2015-01-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Feng Chen ,  Chen-Shien Chen ,  Sheng-Yu Wu ,  Tin-Hao Kuo ,  Yen-Liang Lin

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05011 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05565 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/35121 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01024 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0104 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor device includes a substrate, a semiconductor structure, a metal pad, and a stress releasing material. The semiconductor structure is disposed on the substrate. The metal pad is disposed on the semiconductor structure. The metal pad includes a through hole therein. The stress releasing material is disposed in the through hole.

摘要翻译： 半导体器件包括衬底，半导体结构，金属焊盘和应力释放材料。 半导体结构设置在基板上。 金属焊盘设置在半导体结构上。 金属垫在其中包括一个通孔。 应力释放材料设置在通孔中。