公开(公告)号：US20190074273A1

公开(公告)日：2019-03-07

申请号：US16033252

申请日：2018-07-12

Applicant: Renesas Electronics Corporation

Inventor： Wataru SUMIDA ,  Akihiro SHIMOMURA

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01M10/42 ,  H02J7/00

Abstract: A source electrode can be patterned well in response to the densification of a semiconductor device. A first MOS transistor element is formed in a first element region and a second MOS transistor element is formed in a second element region. A first source electrode is arranged so as to straddle a first gate electrode and cover a first source layer located on both one side and the other side in a gate length direction with the first gate electrode interposed. A second source electrode is arranged so as to straddle a second gate electrode and cover a second source layer located on both one side and the other side in the gate length direction with the second gate electrode interposed.

公开(公告)号：US20190326433A1

公开(公告)日：2019-10-24

申请号：US16374283

申请日：2019-04-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Wataru SUMIDA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: Reliability of a semiconductor device is improved. The semiconductor device including a first MISFET group of a plurality of first MISFETs and a second MISFET group of a plurality of second MISFETs has a plurality of trenches each formed in a semiconductor layer and formed of an upper trench part and a lower trench part, and a plurality of gate electrodes formed inside the plurality of trenches. A thinner gate insulator is formed to the upper trench part and a thicker field insulator is formed to the lower trench part. In a trench at the outermost position in the first MISFET group and a trench at the outermost position in the second MISFET group, the gate insulator is not formed in the upper trench part, but the field insulator is formed in the upper trench part and the lower trench part.

公开(公告)号：US20180047811A1

公开(公告)日：2018-02-15

申请号：US15797519

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Wataru SUMIDA ,  Akihiro Shimomura

IPC: H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device manufacturing method includes preparing a semiconductor substrate of a first conductivity type, forming a semiconductor layer of the first conductivity type over a main surface of the semiconductor substrate, forming a plurality of first ditches in an upper surface portion of the semiconductor layer such that the first ditches are arranged in a first direction extending along an upper surface of the semiconductor substrate, forming a plurality of second ditches in bottom surface portions of each of the first ditches such that the second ditches are arranged in a second direction perpendicular to the first direction, and covering a side wall of each of the first ditches with a first insulating film and a side wall and a bottom surface of each of the second ditches with a second insulating film thicker than the first insulating film.