公开(公告)号：US20180349208A1

公开(公告)日：2018-12-06

申请号：US16100260

申请日：2018-08-10

Applicant: Renesas Electronics Corporation

Inventor： Tetsuji TSUDA ,  Masaru HASE ,  Yuki INOUE ,  Naohiro NISHIKAWA

IPC: G06F9/52 ,  G06F9/48

CPC classification number: G06F9/52 ,  G06F9/4812

Abstract: A semiconductor device includes a central processing unit and a processor on one semiconductor substrate. The processor includes a buffer for storing a first register setting list and notifies the central processing unit of an access complete signal indicating completion of reading a second register setting list within a memory. The central processing unit changes the second register setting list within the memory based on the access complete signal and notifies the processor of an update request signal. The processor reads the second register setting list changed by the central processing unit into the buffer to update the first register setting list based on the update request information.

公开(公告)号：US20180041357A1

公开(公告)日：2018-02-08

申请号：US15631284

申请日：2017-06-23

Applicant: Renesas Electronics Corporation

Inventor： Tetsuji TSUDA ,  Masaru HASE ,  Yuki INOUE ,  Katsushige MATSUBARA

IPC: H04L12/28 ,  G11C5/04 ,  G11C29/02 ,  G06F11/30

CPC classification number: H04L12/2856 ,  G06F11/3034 ,  G11C5/04 ,  G11C29/025 ,  H01L2224/16 ,  H01L2924/1305

Abstract: A semiconductor device includes a plurality of IP cores, a plurality of storage devices, a configuration information acquiring unit that acquires configuration information for specifying a timing when the IP core accesses the storage device, and an allocation determining unit that determines the storage device allocated to the IP core. The configuration information acquiring unit acquires configuration information regarding a first IP core and configuration information regarding a second IP core. The allocation determining unit determines, based on the configuration information, whether an access timing by the first IP core is the same as an access timing by the second IP core, and when it is determined that the access timings are the same, determines allocation in such a way that the storage device allocated to the first IP core becomes different from the storage device allocated to the second IP core.

公开(公告)号：US20170161219A1

公开(公告)日：2017-06-08

申请号：US15357212

申请日：2016-11-21

Applicant: Renesas Electronics Corporation

Inventor： Masaru HASE ,  Tetsuji TSUDA ,  Naohiro NISHIKAWA ,  Yuki INOUE ,  Seiji MOCHIZUKI ,  Katsushige MATSUBARA ,  Ren IMAOKA

IPC: G06F13/362 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/4022 ,  G06F15/17312 ,  G06F15/7807

Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced.The semiconductor device includes a CPU section. and a. hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.