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公开(公告)号：US09025701B2
公开(公告)日：2015-05-05
申请号：US14183462
申请日：2014-02-18
发明人： Keiichi Itoigawa , Shinichi Ogou , Jun Kurosawa , Takashi Tamura
CPC分类号： H04L25/0272 , H04L7/0008 , H04L7/0037 , H04L7/0041 , H04L7/0338 , H04L7/04 , H04L25/14
摘要： A receiver is composed of a receiver-side amplifier which receives a clock signal, a receiver-side amplifier which receives a data signal, a variable delay circuit which generates a delay-adjusted clock signal and a delay-adjusted data signal by delaying the clock signal and the data signal, a latch circuit section which latches the delay-adjusted data signal in synchronous with the delay-adjusted clock signal, and a skew detecting circuit which generates skew detection data that by latching a specific data sequence transmitted as the data signal in synchronous with a first clock signal to Nth clock signal (N is an integer equal to or more than 2) with different delay times from the clock signal. The delay time in the variable delay circuit is controlled according to the skew detection data.
摘要翻译： 接收机由接收时钟信号的接收机侧放大器，接收数据信号的接收机侧放大器，延迟调整后的时钟信号的可变延迟电路和延迟调整后的数据信号构成 信号和数据信号，锁存电路部分，其与经延迟调整的时钟信号同步地锁存延迟调整的数据信号，以及偏斜检测电路，其产生通过锁存作为数据信号发送的特定数据序列的偏移检测数据 与来自时钟信号的不同延迟时间的第一时钟信号至第N时钟信号（N为等于或大于2的整数）同步。 可变延迟电路中的延迟时间根据偏斜检测数据进行控制。
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公开(公告)号：US20140241465A1
公开(公告)日：2014-08-28
申请号：US14183462
申请日：2014-02-18
发明人： Keiichi Itoigawa , Shinichi Ogou , Jun Kurosawa , Takashi Tamura
IPC分类号： H04L25/40
CPC分类号： H04L25/0272 , H04L7/0008 , H04L7/0037 , H04L7/0041 , H04L7/0338 , H04L7/04 , H04L25/14
摘要： A receiver is composed of a receiver-side amplifier which receives a clock signal, a receiver-side amplifier which receives a data signal, a variable delay circuit which generates a delay-adjusted clock signal and a delay-adjusted data signal by delaying the clock signal and the data signal, a latch circuit section which latches the delay-adjusted data signal in synchronous with the delay-adjusted clock signal, and a skew detecting circuit which generates skew detection data that by latching a specific data sequence transmitted as the data signal in synchronous with a first clock signal to Nth clock signal (N is an integer equal to or more than 2) with different delay times from the clock signal. The delay time in the variable delay circuit is controlled according to the skew detection data.
摘要翻译： 接收机由接收时钟信号的接收机侧放大器，接收数据信号的接收机侧放大器，延迟调整后的时钟信号的可变延迟电路和延迟调整后的数据信号构成 信号和数据信号，锁存电路部分，其与经延迟调整的时钟信号同步地锁存延迟调整的数据信号，以及偏斜检测电路，其产生通过锁存作为数据信号发送的特定数据序列的偏移检测数据 与来自时钟信号的不同延迟时间的第一时钟信号至第N时钟信号（N为等于或大于2的整数）同步。 可变延迟电路中的延迟时间根据偏斜检测数据进行控制。
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