公开(公告)号：US4050058A

公开(公告)日：1977-09-20

申请号：US625627

申请日：1975-10-24

Applicant: Richard A. Garlic

Inventor： Richard A. Garlic

IPC: G06F9/22 ,  G06F13/34 ,  G06F15/16 ,  G06F15/78 ,  G06F3/00

CPC classification number: G06F9/22 ,  G06F13/34 ,  G06F15/16 ,  G06F15/7864

Abstract: A highly parallel microprocessor using a logic gating structure and a microinstruction organization which permits direct access by each of the microprocessor components to a tri-bus system. Operation is defined by a single phase clock, during which all portions of a microinstruction are executed. The system further permits overlap operation for microprocessor instructions, thereby allowing for the fetching of a next instruction while executing a current instruction. The use of general purpose, non-dedicated registers is contemplated, thereby to avoid the need for multi-phase clocking.

Abstract translation: 使用逻辑门控结构和微指令组织的高度并行微处理器，其允许每个微处理器组件直接访问三总线系统。 操作由单相时钟定义，在此期间执行微指令的所有部分。 该系统进一步允许微处理器指令的重叠操作，从而允许在执行当前指令时取出下一条指令。 考虑使用通用非专用寄存器，从而避免了对多相时钟的需要。

公开(公告)号：US3938098A

公开(公告)日：1976-02-10

申请号：US428597

申请日：1973-12-16

Applicant: Richard A. Garlic

Inventor： Richard A. Garlic

IPC: G06F3/00 ,  G06F13/34 ,  G06F9/06

CPC classification number: G06F13/34

Abstract: A microprogrammable data processor comprising a generalized three-bus archictecture wherein the functional processing elements are connected between the busses by means of tri-state logic elements which allow the elements to selectively drive, receive from, or present a high impedance to the busses under control of a microprogram. The device includes an input-output system in which the input/output device may have access to all three busses, two for data and for address inputs and the third for receiving output data. The busses may be multifunction busses for carrying either data or address signals.The device utilizes a single phase clock and performs operations in a highly parallel manner.TABLE OF CONTENTSAbstract of the DisclosureBackground of the InventionField of the InventionDescription of the Prior ArtSummary of the InventionBrief Description of the DrawingsDetailed Description of a Preferred EmbodimentSystem OrganizationInstruction FlowData FlowArithmetic and Logic Unit (ALU)General RegistersStatusInput/OutputScratch Pads/Main MemoryTranslatorMaintenance Control PanelInformation Flow: SummaryInterrupt FlowMicroinstruction RepertoireSingle Purpose Micro FieldsMultiple Purpose FieldsWord/Byte OperationSet/Reset/Test A BitAddressing and BranchingSample MicroprogramSystem Input/OutputI/o interrupt

Abstract translation: 一种可编程数据处理器，包括一般化的三总线架构，其中功能处理元件通过三态逻辑元件连接在总线之间，三态逻辑元件允许这些元件选择性地驱动，接收或呈现对控制下的总线的高阻抗 的微程序。 该设备包括输入/​​输出系统，其中输入/输出设备可以访问所有三个总线，两个用于数据和地址输入，第三个用于接收输出数据。 总线可以是用于承载数据或地址信号的多功能总线。

公开(公告)号：US3943495A

公开(公告)日：1976-03-09

申请号：US428632

申请日：1973-12-26

Applicant: Richard A. Garlic

Inventor： Richard A. Garlic

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/35 ,  G06F9/455 ,  G06F9/00

CPC classification number: G06F9/261 ,  G06F9/262

Abstract: A microprocessor with a bus structure for carrying address and data signals wherein an address may be modified by an index value for indirect addressing by deriving said index value from an index register or a control word field. Immediate addressing is provided on branch instructions by providing two separate incrementing paths to avoid loss of a machine cycle during branch.

Abstract translation: 具有用于承载地址和数据信号的总线结构的微处理器，其中可以通过从索引寄存器或控制字字段导出所述索引值的间接寻址的索引值来修改地址。 通过提供两个单独的递增路径，在分支指令中提供立即寻址，以避免分支期间机器周期的损失。