公开(公告)号：US5761065A

公开(公告)日：1998-06-02

申请号：US413990

申请日：1995-03-30

申请人： Richard Charles Kittler ,  Zhi-Min Ling ,  James Minsu Pak ,  Yung-Tao Lin ,  Ying Shiau

发明人： Richard Charles Kittler ,  Zhi-Min Ling ,  James Minsu Pak ,  Yung-Tao Lin ,  Ying Shiau

IPC分类号： G05B19/418 ,  H01L21/66 ,  C07C2/68

CPC分类号： H01L22/20 ,  G05B19/41875 ,  G05B2219/31282 ,  G05B2219/31318 ,  G05B2219/45026 ,  Y02P90/22

摘要： An arrangement and method for detecting sequential processing effects on devices to be manufactured in a manufacturing process extracts data regarding responses of the devices to a process step in the manufacturing process and data regarding a processing sequence of the devices in that process step. The extracted data is refined before analysis and control chart rules are then applied to the refined data. These control chart rules detect whether there are any unusual processing effects caused by the sequence of processing of the devices in any one of the individual processing steps. Application of control chart rules to the refined data allows an automatic determination of whether there are any rule violations. One or more control charts which have a rule violation are automatically generated when it is determined that there is a rule violation. Process engineers may then use the automatically generated charts to direct their efforts at improving the manufacturing process.

摘要翻译： 用于检测在制造过程中要制造的装置的顺序处理效果的布置和方法将关于装置的响应的数据提取到制造过程中的处理步骤以及关于该处理步骤中的装置的处理顺序的数据。 提取的数据在分析之前进行细化，然后将控制图规则应用于精炼数据。 这些控制图规则检测在各个处理步骤中的任何一个处理装置的处理序列是否存在异常的处理效果。 将控制图规则应用于精细数据允许自动确定是否存在违规规则。 当确定存在规则违规时，会自动生成一个或多个具有规则违规的控制图。 然后，过程工程师可以使用自动生成的图表来指导他们改进制造过程。

公开(公告)号：US5963780A

公开(公告)日：1999-10-05

申请号：US899739

申请日：1997-07-24

申请人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

发明人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

IPC分类号： H01L23/544 ,  H01L21/66 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively silicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

摘要翻译： 用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置和方法及其制造方法。 实现的是双桥测试结构，其包括第一半导体材料的电阻器路径，例如包括多个条带段和互连段的掺杂硅。 连接具有基本上较低电阻率的多个第二半导体材料带，以形成与相应条带段的并联电路互连。 测试结构通过掩模技术形成，其中规定的掩模区域使得硅电阻器或沉积的多晶硅的部分分别被选择性地硅化以形成硅化物和多硅化物。 用于测试多晶硅层中的缺陷的一个实施例使用聚硅氧烷作为低电阻率带，能够测试开路和短路缺陷。 第二实施例选择性地硅化源极 - 漏极电阻器的暴露部分，从而能够测试金属氧化物半导体的源极 - 漏极层中的缺陷。 通过将测得的电阻值与条的预定宽度和间距进行比较来确定缺陷尺寸。

公开(公告)号：US5716856A

公开(公告)日：1998-02-10

申请号：US517960

申请日：1995-08-22

申请人： Yung-Tao Lin ,  Zhi-Min Ling ,  James Pak ,  Ying Shiau

发明人： Yung-Tao Lin ,  Zhi-Min Ling ,  James Pak ,  Ying Shiau

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  Y10S148/162

摘要： An arrangement and method for detecting sequential processing effects on products to be manufactured in a manufacturing process orders a first set of the products in a first specified processing sequence for a first process step in the manufacturing process. In order to prevent any positional trend created at one process step from being carried over into the next process step, the first set of the products is re-ordered into a second, different specified processing sequence for a second process step in the manufacturing process. Data regarding responses of the first set of the products to the process steps are extracted. The extracted data are correlated with the first and second processing sequences and data analysis is performed on the correlated extracted data. These steps are repeated for subsequent sets of the products, so that although the specified processing sequence is different for each of the individual process steps for a set of products, the same processing sequences for the individual processing steps are used for subsequent sets of the products to be manufactured. Since the processing sequences are not randomized from set to set and do not have to be provided to a database, the amounts of interfacing and disk storage needed are greatly reduced.

公开(公告)号：US5821765A

公开(公告)日：1998-10-13

申请号：US900013

申请日：1997-07-24

申请人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

发明人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

IPC分类号： H01L23/544 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively suicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

摘要翻译： 用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置和方法及其制造方法。 实现的是双桥测试结构，其包括第一半导体材料的电阻器路径，例如包括多个条带段和互连段的掺杂硅。 连接具有基本上较低电阻率的多个第二半导体材料带，以形成与相应条带段的并联电路互连。 测试结构通过掩模技术形成，其中规定的掩模区域使得硅电阻器或沉积的多晶硅的部分分别被选择性地硅化以形成硅化物和多硅化物。 用于测试多晶硅层中的缺陷的一个实施例使用聚硅氧烷作为低电阻率带，能够测试开路和短路缺陷。 第二实施例选择性地使源极 - 漏极电阻器的暴露部分自动化，从而能够测试金属氧化物半导体的源极 - 漏极层中的缺陷。 通过将测得的电阻值与条的预定宽度和间距进行比较来确定缺陷尺寸。

公开(公告)号：US6001663A

公开(公告)日：1999-12-14

申请号：US280997

申请日：1999-03-30

申请人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

发明人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

IPC分类号： H01L23/544 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively silicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

摘要翻译： 用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置和方法及其制造方法。 实现的是双桥测试结构，其包括第一半导体材料的电阻器路径，例如包括多个条带段和互连段的掺杂硅。 连接具有基本上较低电阻率的多个第二半导体材料带，以形成与相应条带段的并联电路互连。 测试结构通过掩模技术形成，其中规定的掩模区域使得硅电阻器或沉积的多晶硅的部分分别被选择性地硅化以形成硅化物和多硅化物。 用于测试多晶硅层中的缺陷的一个实施例使用聚硅氧烷作为低电阻率带，能够测试开路和短路缺陷。 第二实施例选择性地硅化源极 - 漏极电阻器的暴露部分，从而能够测试金属氧化物半导体的源极 - 漏极层中的缺陷。 通过将测得的电阻值与条的预定宽度和间距进行比较来确定缺陷尺寸。

公开(公告)号：US5670891A

公开(公告)日：1997-09-23

申请号：US477384

申请日：1995-06-07

申请人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

发明人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

IPC分类号： H01L23/544 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively silicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

摘要翻译： 用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置和方法及其制造方法。 实现的是双桥测试结构，其包括第一半导体材料的电阻器路径，例如包括多个条带段和互连段的掺杂硅。 连接具有基本上较低电阻率的多个第二半导体材料带，以形成与相应条带段的并联电路互连。 测试结构通过掩模技术形成，其中规定的掩模区域使得硅电阻器或沉积的多晶硅的部分分别被选择性地硅化以形成硅化物和多硅化物。 用于测试多晶硅层中的缺陷的一个实施例使用聚硅氧烷作为低电阻率带，能够测试开路和短路缺陷。 第二实施例选择性地硅化源极 - 漏极电阻器的暴露部分，从而能够测试金属氧化物半导体的源极 - 漏极层中的缺陷。 通过将测得的电阻值与条的预定宽度和间距进行比较来确定缺陷尺寸。

公开(公告)号：US5930138A

公开(公告)日：1999-07-27

申请号：US926487

申请日：1997-09-10

申请人： Yung-Tao Lin ,  Zhi-Min Ling ,  James Pak ,  Ying Shiau

发明人： Yung-Tao Lin ,  Zhi-Min Ling ,  James Pak ,  Ying Shiau

IPC分类号： H01L21/66 ,  G06F19/00 ,  G06G7/64 ,  G06G7/66

CPC分类号： H01L22/20 ,  Y10S148/162

摘要： An arrangement and method for detecting sequential processing effects on products to be manufactured in a manufacturing process orders a first set of the products in a first specified processing sequence for a first process step in the manufacturing process. In order to prevent any positional trend created at one process step from being carried over into the next process step, the first set of the products is re-ordered into a second, different specified processing sequence for a second process step in the manufacturing process. Data regarding responses of the first set of the products to the process steps are extracted. The extracted data are correlated with the first and second processing sequences and data analysis is performed on the correlated extracted data. These steps are repeated for subsequent sets of the products, so that although the specified processing sequence is different for each of the individual process steps for a set of products, the same processing sequences for the individual processing steps are used for subsequent sets of the products to be manufactured. Since the processing sequences are not randomized from set to set and do not have to be provided to a database, the amounts of interfacing and disk storage needed are greatly reduced.

摘要翻译： 用于检测对在制造过程中制造的产品的顺序处理影响的布置和方法，以在制造过程中的第一处理步骤的第一指定处理顺序中对第一组产品进行订购。 为了防止在一个处理步骤中产生的任何位置趋势被转移到下一个处理步骤中，将第一组产品重新排列成制造过程中第二个处理步骤的第二个不同的指定处理顺序。 提取关于第一组产品对处理步骤的响应的数据。 提取的数据与第一和第二处理序列相关，并且对相关的提取数据进行数据分析。 对于随后的产品组重复这些步骤，使得尽管对于一组产品的各个处理步骤的指定处理顺序是不同的，但是用于各个处理步骤的相同处理顺序用于随后的产品集合 被制造。 由于处理序列不是从集合中随机化设置的，并且不必提供给数据库，因此大大减少了所需的接口和磁盘存储量。

公开(公告)号：US5598341A

公开(公告)日：1997-01-28

申请号：US401490

申请日：1995-03-10

申请人： Zhi-Min Ling ,  Thao Vo ,  Siu-May Ho ,  Ying Shiau ,  Yeng-Kaung Peng ,  Yung-Tao Lin

发明人： Zhi-Min Ling ,  Thao Vo ,  Siu-May Ho ,  Ying Shiau ,  Yeng-Kaung Peng ,  Yung-Tao Lin

IPC分类号： G01N21/95 ,  G03F7/20 ,  H01L21/00 ,  H01L21/66 ,  G06F19/00

CPC分类号： H01L21/67288 ,  G01N21/9501 ,  G03F7/705 ,  G03F7/7065 ,  H01L21/67276 ,  H01L22/20

摘要： A real-time in-line defect disposition and yield forecasting system for a semiconductor wafer having layer containing devices includes an in-line fabrication inspection tool, a design review station, and a yield management station. The in-line fabrication inspection tool inspects at least two layers of the semiconductor wafer and produces first information including particle size, particle location and number of particles introduced therein for each of these layers. The design review station inspects the layers of the semiconductor wafer and produces second information including layouts of each of the layers. The yield management station is operatively connected to the in-line fabrication inspection tool and to the design review station. The yield management station retrieves the first information and the second information from the in-line fabrication inspection tool and from the design review station. The yield management station determines at least one of a number of killer defects for the devices in each of the layers or a defect sensitive area index for each of the layers using the first and second information. The yield management station also determines a priority for analyzing each of the at least two layers responsive to at least one of the number of killer defects and the defect sensitive area index for each of the layers.

摘要翻译： 具有层包含装置的半导体晶片的实时在线缺陷布置和产量预测系统包括在线制造检查工具，设计审查站和产量管理站。 在线制造检查工具检查半导体晶片的至少两层，并且产生包括其中为每个这些层引入的颗粒尺寸，颗粒位置和颗粒数量的第一信息。 设计检查站检查半导体晶片的层，并产生包括每个层的布局的第二信息。 产量管理站可操作地连接到在线制造检查工具和设计审查站。 产量管理站从设计检查站检索来自在线制造检验工具的第一信息和第二信息。 收益管理站使用第一和第二信息确定每个层中的设备的多个杀手缺陷中的至少一个或每个层的缺陷敏感区域索引。 收益管理站还根据每个层的凶手缺陷数量和缺陷敏感区域索引中的至少一个来确定分析至少两个层中的每一个的优先级。

公开(公告)号：US06664808B2

公开(公告)日：2003-12-16

申请号：US09924365

申请日：2001-08-07

申请人： Zhi-Min Ling ,  Jae Cho ,  Robert W. Wells ,  Clay S. Johnson ,  Shelly G. Davis

发明人： Zhi-Min Ling ,  Jae Cho ,  Robert W. Wells ,  Clay S. Johnson ,  Shelly G. Davis

IPC分类号： H03K19177

CPC分类号： G01R31/318519

摘要： FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can execute the design accurately even with the localized defect. The FPGA will be marked as suitable for that design if it passes the test. If the FPGA is found to be unsuitable for one design, additional designs may be tested. Thus, a FPGA manufacturer can sell FPGAs that are normally discarded. As a result, the price of these FPGAs could be set significantly low.

公开(公告)号：US07246285B1

公开(公告)日：2007-07-17

申请号：US10815492

申请日：2004-04-01

申请人： Tarek Eldin ,  Zhi-Min Ling ,  Feng Wang ,  David M. Mahoney

发明人： Tarek Eldin ,  Zhi-Min Ling ,  Feng Wang ,  David M. Mahoney

IPC分类号： G01R31/28 ,  G11C29/00

CPC分类号： G01R31/318516 ,  G01R31/31717

摘要： The configuration of a faulty line segment in a switch matrix of a programmable logic device is identified using read-back capture. Each original programmable interconnection point (“PIP”) in the line segment is tested by generating routes from a first logic port through the original line segment and PIP, through all PIPs, adjacent to the original PIP to the opposite logic port. Routes through all PIPs adjacent to the PIPs in the line segment from the first logic port to the second logic port, and from the second logic port to the first logic port, are tested to isolate the fault in the line segment.

摘要翻译： 使用回读捕获识别可编程逻辑器件的开关矩阵中的故障线段的配置。 线段中的每个原始可编程互连点（“PIP”）通过从第一个逻辑端口到原始线段和PIP的路由，通过与原始PIP相邻的所有PIP生成到相对的逻辑端口进行测试。 通过从第一逻辑端口到第二逻辑端口以及从第二逻辑端口到第一逻辑端口的线段中与PIP相邻的所有PIP的路由被测试以隔离线段中的故障。