公开(公告)号：US08343795B2

公开(公告)日：2013-01-01

申请号：US12877953

申请日：2010-09-08

申请人： Yuhao Luo ,  Zhi-min Ling

发明人： Yuhao Luo ,  Zhi-min Ling

IPC分类号： H01L21/00 ,  H01L25/00 ,  B23Q3/00

CPC分类号： H01L31/0547 ,  H01L31/0488 ,  H01L31/0508 ,  Y02B10/10 ,  Y02E10/52

摘要： The present disclosure relates generally to a method to break and assemble solar cells to make solar panel. The present disclosure provides a method to produce solar pieces from solar cell, as well as assemble them together. The present disclosure device is unique when compared with other known devices and solutions because the present disclosure provides a high speed method to break scribed cells into pieces. A method of forming a string of solar cells includes providing a scribe line on a solar cell and placing a first ribbon on the solar cell. The method then includes placing the solar cell on a supporter and then breaking the solar cell into a plurality of solar cell pieces. The method then has the step of placing a second ribbon on the solar cell pieces and soldering the first and second ribbons and the solar cell pieces and then assembling the solar cell pieces into a string of solar cells.

摘要翻译： 本公开一般涉及一种破坏和组装太阳能电池以制造太阳能电池板的方法。 本公开提供了一种从太阳能电池产生太阳能片的方法，以及将它们组装在一起。 本公开的装置与其它已知的装置和解决方案相比是独一无二的，因为本公开提供了一种将划刻的细胞分成碎片的高速方法。 一种形成太阳能电池串的方法包括在太阳能电池上设置划线并将第一带放置在太阳能电池上。 然后，该方法包括将太阳能电池放置在支撑件上，然后将太阳能电池分解成多个太阳能电池片。 然后，该方法具有将第二带状物放置在太阳能电池片上并焊接第一和第二带状物和太阳能电池片的步骤，然后将太阳能电池片组装成太阳能电池组。

公开(公告)号：US06664808B2

公开(公告)日：2003-12-16

申请号：US09924365

申请日：2001-08-07

申请人： Zhi-Min Ling ,  Jae Cho ,  Robert W. Wells ,  Clay S. Johnson ,  Shelly G. Davis

发明人： Zhi-Min Ling ,  Jae Cho ,  Robert W. Wells ,  Clay S. Johnson ,  Shelly G. Davis

IPC分类号： H03K19177

CPC分类号： G01R31/318519

摘要： FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can execute the design accurately even with the localized defect. The FPGA will be marked as suitable for that design if it passes the test. If the FPGA is found to be unsuitable for one design, additional designs may be tested. Thus, a FPGA manufacturer can sell FPGAs that are normally discarded. As a result, the price of these FPGAs could be set significantly low.

公开(公告)号：US5963780A

公开(公告)日：1999-10-05

申请号：US899739

申请日：1997-07-24

申请人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

发明人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

IPC分类号： H01L23/544 ,  H01L21/66 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively silicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

摘要翻译： 用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置和方法及其制造方法。 实现的是双桥测试结构，其包括第一半导体材料的电阻器路径，例如包括多个条带段和互连段的掺杂硅。 连接具有基本上较低电阻率的多个第二半导体材料带，以形成与相应条带段的并联电路互连。 测试结构通过掩模技术形成，其中规定的掩模区域使得硅电阻器或沉积的多晶硅的部分分别被选择性地硅化以形成硅化物和多硅化物。 用于测试多晶硅层中的缺陷的一个实施例使用聚硅氧烷作为低电阻率带，能够测试开路和短路缺陷。 第二实施例选择性地硅化源极 - 漏极电阻器的暴露部分，从而能够测试金属氧化物半导体的源极 - 漏极层中的缺陷。 通过将测得的电阻值与条的预定宽度和间距进行比较来确定缺陷尺寸。

公开(公告)号：US5716856A

公开(公告)日：1998-02-10

申请号：US517960

申请日：1995-08-22

申请人： Yung-Tao Lin ,  Zhi-Min Ling ,  James Pak ,  Ying Shiau

发明人： Yung-Tao Lin ,  Zhi-Min Ling ,  James Pak ,  Ying Shiau

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  Y10S148/162

摘要： An arrangement and method for detecting sequential processing effects on products to be manufactured in a manufacturing process orders a first set of the products in a first specified processing sequence for a first process step in the manufacturing process. In order to prevent any positional trend created at one process step from being carried over into the next process step, the first set of the products is re-ordered into a second, different specified processing sequence for a second process step in the manufacturing process. Data regarding responses of the first set of the products to the process steps are extracted. The extracted data are correlated with the first and second processing sequences and data analysis is performed on the correlated extracted data. These steps are repeated for subsequent sets of the products, so that although the specified processing sequence is different for each of the individual process steps for a set of products, the same processing sequences for the individual processing steps are used for subsequent sets of the products to be manufactured. Since the processing sequences are not randomized from set to set and do not have to be provided to a database, the amounts of interfacing and disk storage needed are greatly reduced.

公开(公告)号：US07246285B1

公开(公告)日：2007-07-17

申请号：US10815492

申请日：2004-04-01

申请人： Tarek Eldin ,  Zhi-Min Ling ,  Feng Wang ,  David M. Mahoney

发明人： Tarek Eldin ,  Zhi-Min Ling ,  Feng Wang ,  David M. Mahoney

IPC分类号： G01R31/28 ,  G11C29/00

CPC分类号： G01R31/318516 ,  G01R31/31717

摘要： The configuration of a faulty line segment in a switch matrix of a programmable logic device is identified using read-back capture. Each original programmable interconnection point (“PIP”) in the line segment is tested by generating routes from a first logic port through the original line segment and PIP, through all PIPs, adjacent to the original PIP to the opposite logic port. Routes through all PIPs adjacent to the PIPs in the line segment from the first logic port to the second logic port, and from the second logic port to the first logic port, are tested to isolate the fault in the line segment.

摘要翻译： 使用回读捕获识别可编程逻辑器件的开关矩阵中的故障线段的配置。 线段中的每个原始可编程互连点（“PIP”）通过从第一个逻辑端口到原始线段和PIP的路由，通过与原始PIP相邻的所有PIP生成到相对的逻辑端口进行测试。 通过从第一逻辑端口到第二逻辑端口以及从第二逻辑端口到第一逻辑端口的线段中与PIP相邻的所有PIP的路由被测试以隔离线段中的故障。

公开(公告)号：US06891395B2

公开(公告)日：2005-05-10

申请号：US10853981

申请日：2004-05-25

申请人： Robert W. Wells ,  Zhi-Min Ling ,  Robert D. Patrie ,  Vincent L. Tong ,  Jae Cho ,  Shahin Toutounchi

发明人： Robert W. Wells ,  Zhi-Min Ling ,  Robert D. Patrie ,  Vincent L. Tong ,  Jae Cho ,  Shahin Toutounchi

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F17/50 ,  H01L21/82 ,  H03K19/173

CPC分类号： G01R31/318519 ,  G06F17/5054

摘要： Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.

摘要翻译： 公开了利用包含至少一个局部缺陷的可编程逻辑器件的方法。 这些设备被测试以确定它们适用于实现可能不需要受缺陷影响的资源的选定设计。 如果发现FPGA不适合于一个设计，则可以测试其他设计。 在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。 测试电路允许PLD供应商验证PLD对给定用户设计的适用性，而不需要PLD供应商了解用户的设计。

公开(公告)号：US5821765A

公开(公告)日：1998-10-13

申请号：US900013

申请日：1997-07-24

申请人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

发明人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

IPC分类号： H01L23/544 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively suicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

摘要翻译： 用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置和方法及其制造方法。 实现的是双桥测试结构，其包括第一半导体材料的电阻器路径，例如包括多个条带段和互连段的掺杂硅。 连接具有基本上较低电阻率的多个第二半导体材料带，以形成与相应条带段的并联电路互连。 测试结构通过掩模技术形成，其中规定的掩模区域使得硅电阻器或沉积的多晶硅的部分分别被选择性地硅化以形成硅化物和多硅化物。 用于测试多晶硅层中的缺陷的一个实施例使用聚硅氧烷作为低电阻率带，能够测试开路和短路缺陷。 第二实施例选择性地使源极 - 漏极电阻器的暴露部分自动化，从而能够测试金属氧化物半导体的源极 - 漏极层中的缺陷。 通过将测得的电阻值与条的预定宽度和间距进行比较来确定缺陷尺寸。

公开(公告)号：US20110088743A1

公开(公告)日：2011-04-21

申请号：US12904972

申请日：2010-10-14

申请人： Yuhao Luo ,  Zhi-min Ling

发明人： Yuhao Luo ,  Zhi-min Ling

IPC分类号： H01L31/042

CPC分类号： H02S50/00

摘要： An apparatus and method relates to managing and controlling a photovoltaic system, especially for the safety, maintenance, alert of theft, and connection failure of the system. It is more specially for cases during the night time when the panel is not generating electricity. The present disclosure provides: an AC panel, an inverter; a communication circuit in a panel inverter to send and receive signals, a control circuit, a communicator and a power line communication method between communicator and panel inverters. The communicator detects an identification of each panel to identify the panels and collect data from each panel. The communicator is connected to the Internet through a web gateway. The apparatus also has a web based managing system to collect data from the communicator, as well as transmit signals to the communicator.

摘要翻译： 一种装置和方法涉及管理和控制光伏系统，特别是用于安全，维护，盗窃警报和系统的连接故障。 特别是在面板不发电的夜晚的情况下。 本公开提供：AC面板，逆变器; 通信器和面板逆变器之间的发送和接收信号的面板反相器中的通信电路，控制电路，通信器和电力线通信方法。 通信器检测每个面板的识别，以识别面板并从每个面板收集数据。 通信器通过网关连接到互联网。 该装置还具有基于网络的管理系统以从通信器收集数据，以及向通信器发送信号。

公开(公告)号：US20110017263A1

公开(公告)日：2011-01-27

申请号：US12205574

申请日：2008-09-05

申请人： KEVIN R. GIBSON ,  NEELSEN CO ,  ZHI-MIN LING ,  CHRIS MIHAI ,  ALELIE FUNCELL ,  RAMON ROSAL REGLOS

发明人： KEVIN R. GIBSON ,  NEELSEN CO ,  ZHI-MIN LING ,  CHRIS MIHAI ,  ALELIE FUNCELL ,  RAMON ROSAL REGLOS

IPC分类号： H01L31/042 ,  H01L31/18

CPC分类号： H01L31/022433 ,  H01L31/035281 ,  H01L31/042 ,  H01L31/0543 ,  H01L31/18 ,  Y02E10/52

摘要： A method and device of fabricating a photovoltaic strip. The method includes providing a photovoltaic cell having a front surface and a back surface and forming a first grid pattern on the front surface and second grid pattern on the back surface. The first grid pattern includes a first plurality of strip columns in parallel in a first direction and a plurality of grid lines in parallel in a second direction perpendicularly crossing the first plurality of strip columns. The second grid pattern includes a plurality of blocks separated by a plurality of streets parallel in the second direction and a second plurality of strip columns parallel in the first direction. The method further includes dicing the photovoltaic cell along the plurality of streets into a plurality of photovoltaic strips. Each of the plurality of photovoltaic strips includes at least one of the plurality of grid lines.

摘要翻译： 一种制造光伏带的方法和装置。 该方法包括提供具有前表面和后表面的光伏电池，并且在前表面上形成第一格栅图案，并在背面上形成第二格栅图案。 第一格栅图案包括沿第一方向平行的第一多个条状列和与垂直于第一多个条形列垂直的第二方向平行的多个栅格线。 第二格栅图案包括由在第二方向上平行的多个街道分开的多个块，以及在第一方向上平行的第二多个条形列。 该方法还包括沿多个街道将光伏电池切割成多个光伏条。 多个光伏条中的每一个包括多个网格线中的至少一个。

公开(公告)号：US07227364B1

公开(公告)日：2007-06-05

申请号：US11016473

申请日：2004-12-16

申请人： Yuezhen Fan ,  David Mark ,  Eric J Thorne ,  Zhi-Min Ling

发明人： Yuezhen Fan ,  David Mark ,  Eric J Thorne ,  Zhi-Min Ling

IPC分类号： G01R31/28 ,  G01R31/26

CPC分类号： G01R31/318516 ,  G01R31/31717 ,  G01R31/31855

摘要： The embodiments of the present invention enable a new metal diagnosis pattern based on a production test pattern to quickly identify open and short circuits of metal lines which cannot be probed, such as the long lines of a programmable logic device, and to further isolates the fault location for physical failure analysis. According to one aspect of the invention, a circuit locally drives a plurality of metal long line segments to determine whether a defect in a line is a short circuit, or further to identify the location of an open circuit.

摘要翻译： 本发明的实施例使得能够基于生产测试图案的新的金属诊断模式快速识别不能探测的金属线的开路和短路，例如可编程逻辑器件的长线，并进一步隔离故障 物理故障分析的位置。 根据本发明的一个方面，电路局部地驱动多个金属长线段以确定线路中的缺陷是短路还是进一步识别开路的位置。