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公开(公告)号：US4035779A
公开(公告)日：1977-07-12
申请号：US681985
申请日：1976-04-30
申请人： Richard Eugene Birney , Michael Ian Davis , Robert Allen Hood , Thomas Stephen McDermott , Larry Edward Wise
发明人： Richard Eugene Birney , Michael Ian Davis , Robert Allen Hood , Thomas Stephen McDermott , Larry Edward Wise
CPC分类号： G06F12/1458
摘要： System mode controls for obtaining limited addressability for supervisor programming operations without disturbing a user address key currently contained in a user key register (UKR).The mode controls are provided by bits in a system register called a level status register (LSR), which include an APM bit, and a supervisor state bit. The largest supervisor addressability is obtained when both the APM and supervisor state bits are set on, which permits execution of a supervisor program which can access user data and programs. In more detail, each instruction fetch must be in the supervisor key area, identified by a predetermined supervisor key value which is not in the UKR, while each operand of the fetched supervisor instruction is accessed in the user key area identified by the current key in the UKR. The supervisor is not permitted to access any user area which does not have its key in the UKR. Thus, the supervisor can be prevented from having addressability over part or all of the main memory.However, if the APM bit is off while the supervisor bit is on, all instruction and operand storage accesses can only be made in the supervisor key area, regardless of whether the supervisor key or user key is in the UKR. Hence no user area is accessible to the supervisor.But, if the supervisor bit is off, all instruction and operand accesses can only be made in the user area of the key in the UKR. Hence the supervisor programs cannot execute.
摘要翻译： 系统模式控制，用于在不干扰当前包含在用户密钥寄存器（UKR）中的用户地址密钥的情况下获得用于管理程序编程操作的有限寻址能力。
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公开(公告)号：US4037215A
公开(公告)日：1977-07-19
申请号：US682222
申请日：1976-04-30
申请人： Richard Eugene Birney , Michael Ian Davis , Robert Allen Hood , Lynn Allan Graybiel , Samuel Kahn , William Steese Osborne
发明人： Richard Eugene Birney , Michael Ian Davis , Robert Allen Hood , Lynn Allan Graybiel , Samuel Kahn , William Steese Osborne
CPC分类号： G06F12/0292
摘要： Active address keys (AAK) are translated into respective addressabilities in physical main memory. Each addressability comprises one or more physical blocks which may be scattered in the main memory. Each address key represents the assigned addressability in main memory for a logical address space. Plural key register sections may be loaded with the same or different address keys. For each storage access request, received from a processor or I/O channel, AAK select circuits outgate to the translator the key in the key register section corresponding to the type of the current storage access request to determine the addressability available to the access request. Each address key identifies a particular stack of one or more segmentation registers. Each segmentation register can be assigned the address of any segment (i.e. a block of contiguous physical addresses located anywhere in the main memory). Each segmentation register also has validity and read-only flag bits for its assigned block. Each stack can translate a contiguous set of logical addresses into physical addresses. For each storage access request for a logical address, and not apparent to the usury program, a stack is addressed by the AAK to translate the logical address to a real address within the assigned addressability. Then a register in the stack is selected by high-order bits in the logical address. The addressed register outputs an assigned block address. Low order bits in the logical address select a byte address in the assigned block. The main memory can have any physical size, which is coordinated with the number of stacks, and to the number of segmentation registers in each stack.
摘要翻译： 活动地址键（AAK）被转换为物理主存储器中的相应地址。 每个可寻址性包括一个或多个可能分散在主存储器中的物理块。 每个地址密钥表示逻辑地址空间在主存储器中分配的可寻址性。 多个密钥寄存器部分可以被加载相同或不同的地址密钥。 对于从处理器或I / O通道接收的每个存储访问请求，AAK选择电路向翻译器输出与当前存储访问请求的类型相对应的密钥寄存器部分中的密钥，以确定可用于访问请求的可寻址性。 每个地址密钥标识一个或多个分段寄存器的特定堆栈。 可以为每个分段寄存器分配任何段的地址（即位于主存储器中任何地方的连续物理地址的块）。 每个分段寄存器还具有其分配块的有效性和只读标志位。 每个堆栈可以将一组连续的逻辑地址转换为物理地址。 对于逻辑地址的每个存储访问请求，并且对于高利率程序而言并不明显，由AAK寻址堆栈，以将逻辑地址转换为所分配的可寻址性内的真实地址。 然后，逻辑地址中的高位选择堆栈中的寄存器。 寻址的寄存器输出分配的块地址。 逻辑地址中的低位位选择分配块中的一个字节地址。 主存储器可以具有与堆栈数量协调的任何物理大小以及每个堆栈中的分段寄存器的数量。
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公开(公告)号：US4042913A
公开(公告)日：1977-08-16
申请号：US681982
申请日：1976-04-30
申请人： Richard Eugene Birney , Michael Ian Davis , Lynn Allan Graybiel , Robert Allen Hood , Samuel Kahn , William Steese Osborne
发明人： Richard Eugene Birney , Michael Ian Davis , Lynn Allan Graybiel , Robert Allen Hood , Samuel Kahn , William Steese Osborne
CPC分类号： G06F9/30043 , G06F12/1458 , G06F13/122
摘要： The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.
摘要翻译： 本公开描述了用于将地址键值加载或存储在键控寄存器控制的寻址系统中的一个或多个地址密钥寄存器部分中的指令操作控制。 该控制装置将处理器中的地址键寄存器（AKR）的一个或所有关键寄存器部分加载或存储在主存储器或通用寄存器（GPR）中的字中。 加载或存储控制都以相同的指令格式操作，其中一个字段指示操作是否是指定的AKR部分的加载或存储。 另一个字段指定要加载或存储的一个AKR部分或所有AKR部分。 还有一个字段指定操作是从主存储器还是从主存储器或GPR。 本公开提供了利用微码操作以执行这些操作的电路。
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公开(公告)号：US4037214A
公开(公告)日：1977-07-19
申请号：US681984
申请日：1976-04-30
IPC分类号： G06F11/00 , G06F12/00 , G06F12/06 , G06F12/14 , G06F15/16 , G06F15/177 , G06F21/24 , G06F13/00
CPC分类号： G06F12/1458 , G06F12/0623
摘要： A plurality of key register sections in a processor respectively associated with different machine-sensed types of accesses to a main storage of a computer system. A processor address key register (AKR) includes the following sections: (1) a section associated with an instruction-fetch type access, (2) a section associated with a source-operand fetch type access, and (3) a section associated with a sink-operand store/fetch type access. Other key register sections may be associated with respective sub-channel store/fetch type accesses. Circuits are provided which sense the different access types to select and outgate a key contained in the corresponding key register section.The values of the keys are associated with different addressabilities (i.e. address spaces). Each different key value is associated with a different stack of translation registers for containing the block addresses in real storage currently assigned to the respective addressabilities.Each key outgated from a respective register section selects an address space by selecting the associated stack of addressing registers to relocatably translate a logical address to a physical storage location within the address space selected by the outgated key.
摘要翻译： 处理器中的多个键寄存器部分分别与对计算机系统的主存储器的不同的机器感测类型的访问相关联。 处理器地址密钥寄存器（AKR）包括以下部分：（1）与指令获取类型访问相关的部分，（2）与源操作数获取类型访问相关联的部分，以及（3）与 一个sink操作数存储/获取类型访问。 其他关键寄存器部分可以与相应的子信道存储/获取类型访问相关联。 提供了检测不同访问类型以选择和打开包含在相应的密钥寄存器部分中的密钥的电路。
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公开(公告)号：US4050060A
公开(公告)日：1977-09-20
申请号：US682221
申请日：1976-04-30
CPC分类号： G06F12/1458 , G06F12/0623
摘要： The disclosure describes equate operand spaces (EOS) control over the addressabilities accessed by means of different address keys in an address key register (AKR) in a processor. Executing instructions, and their source and sink type operands may have different address keys in the AKR, and therefore different addressabilities. When enabled, the EOS control forces each source operand fetch to occur within the sink operand addressability specified in the AKR, even though the AKR explicitly contains a different addressability for source operands. When the EOS feature is disabled, the source operand addressability contained in the AKR is used when fetching source operands. An EOS field in the AKR stores whether the EOS state is enabled or disabled in the processor.
摘要翻译： 本公开描述了对通过处理器中的地址密钥寄存器（AKR）中的不同地址键访问的寻址能力的等效操作数空间（EOS）控制。 执行指令及其源和宿类型操作数可能在AKR中具有不同的地址密钥，因此具有不同的寻址能力。 启用时，EOS控制强制每个源操作数提取发生在AKR指定的宿操作数可寻址性内，即使AKR明确地包含了源操作数的不同寻址能力。 当禁用EOS功能时，在获取源操作数时使用AKR中包含的源操作数可寻址性。 AKR中的EOS字段存储处理器中是否启用EOS状态。
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公开(公告)号：US4038645A
公开(公告)日：1977-07-26
申请号：US682224
申请日：1976-04-30
CPC分类号： G06F12/1458
摘要： Combines a storage protect key stack with an access key register (AKR) and active access key (AAK) select circuits. Storage key entries in the stack correspond to the physical blocks in main memory. This combination can provide storage protection for different storage access types within address sub-ranges in the main memory associated with respective access keys. The sub-ranges are blocks of addresses within the full range of addresses of the physical memory. The protect key operation applies to physical addresses, and it obtains system addressing compatibility with an address translation operation using the same access keys as address keys with program logical addresses.Special features include a shared protect key, which need not be loaded in the AKR, to make specified sub-range(s) shareable by all users of the system, so that any user can access the blocks in memory associated with the shared protect key. For I/O accesses, an override is provided which ignores any read-only control of any memory block to which an I/O access is requested. Supervisor accesses can be made in all key areas, regardless of the AAK, the protect keys, or the read-only flag bits.
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7.发明授权
公开(公告)号：US4084254A
公开(公告)日：1978-04-11
申请号：US792078
申请日：1977-04-28
CPC分类号： G06F7/535 , G06F2207/5353
摘要： A carry save adder (CSA) is adapted for use in dividing operations by providing it with a lookahead capability whereby it accurately predicts whether or not each of the proposed complemental subtractions in a division process could be successfully performed if actually attempted, and it actually performs only those subtractions that will not result in overdrafts. Each bit position of the carry save adder is arranged to receive sum, carry and data inputs and to furnish sum, carry, presum and precarry outputs. The sum and carry output bits are latched and remain undisturbed until the next complemental subtraction is performed. The presum and precarry bits are not latched and are fed into a lookahead logic network which analyzes the presum and precarry bit patterns derived from all of the CSA bit positions to determine rapidly by a logical trial procedure whether the divisor could be subtracted from the dividend or partial remainder value currently registered in the sum and carry latches of the CSA without causing an overdraft. While this trial procedure is in progress, the presum and precarry values may change without altering the latched sum and carry values. If the trial procedure indicates that a proposed complemental subtraction would be unsuccessful, then such subtraction will be skipped without actually being performed by the CSA, thus eliminating the necessity of determining whether overdrafts have occurred and correcting the overdrafts.
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公开(公告)号：US4037207A
公开(公告)日：1977-07-19
申请号：US682226
申请日：1976-04-30
CPC分类号： G06F9/461
摘要： A control circuit arrangement for storing the addressability defined by the current active address key (AAK) being accessed in an address key register (AKR) in a processor. This AAK is stored in a last AAK register. When a hard or soft check interrupt occurs, the AAK stored in the last AAK register is designated as the processor's last key saved (i.e. LKSA) to define an interrupted addressability being used by the processor at the time of an interrupt. Upon occurrence of an interrupt, the LSKA represents the interrupted addressability, which is then made available to the processor by gating the LKSA into a source operand key section in the AKR from the processor's last AAK register, and setting the key for a supervisor program into another section of the AKR, so that the supervisor program can take corrective or termination actions. Until the LKSA gating into the AKR is completed, no AAK can be ingated into the last AAK register. After this in gating to the AKR is completed, the ingating disablement to the last AAK register is released.
摘要翻译： 一种用于存储由在处理器中的地址密钥寄存器（AKR）中被访问的当前活动地址密钥（AAK）定义的可寻址性的控制电路装置。 该AAK存储在最后一个AAK寄存器中。 当发生硬或软检查中断时，存储在最后一个AAK寄存器中的AAK被指定为处理器的最后一个保存的密钥（即LKSA），以定义处理器在中断时使用的中断寻址能力。 在发生中断时，LSKA表示中断的寻址能力，然后通过从处理器的最后一个AAK寄存器中将LKSA门控到AKR中的源操作数键区，然后将管理程序的密钥设置为 AKR的另一部分，以便主管程序可以采取纠正或终止动作。 在LKSA进入AKR之前，在最后一个AAK寄存器中不能输入AAK。 此后，AKR的门控完成后，将释放最后一个AAK寄存器的禁用。
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