公开(公告)号：US4035779A

公开(公告)日：1977-07-12

申请号：US681985

申请日：1976-04-30

申请人： Richard Eugene Birney ,  Michael Ian Davis ,  Robert Allen Hood ,  Thomas Stephen McDermott ,  Larry Edward Wise

发明人： Richard Eugene Birney ,  Michael Ian Davis ,  Robert Allen Hood ,  Thomas Stephen McDermott ,  Larry Edward Wise

IPC分类号： G06F12/06 ,  G06F12/14 ,  G06F13/00

CPC分类号： G06F12/1458

摘要： System mode controls for obtaining limited addressability for supervisor programming operations without disturbing a user address key currently contained in a user key register (UKR).The mode controls are provided by bits in a system register called a level status register (LSR), which include an APM bit, and a supervisor state bit. The largest supervisor addressability is obtained when both the APM and supervisor state bits are set on, which permits execution of a supervisor program which can access user data and programs. In more detail, each instruction fetch must be in the supervisor key area, identified by a predetermined supervisor key value which is not in the UKR, while each operand of the fetched supervisor instruction is accessed in the user key area identified by the current key in the UKR. The supervisor is not permitted to access any user area which does not have its key in the UKR. Thus, the supervisor can be prevented from having addressability over part or all of the main memory.However, if the APM bit is off while the supervisor bit is on, all instruction and operand storage accesses can only be made in the supervisor key area, regardless of whether the supervisor key or user key is in the UKR. Hence no user area is accessible to the supervisor.But, if the supervisor bit is off, all instruction and operand accesses can only be made in the user area of the key in the UKR. Hence the supervisor programs cannot execute.

摘要翻译： 系统模式控制，用于在不干扰当前包含在用户密钥寄存器（UKR）中的用户地址密钥的情况下获得用于管理程序编程操作的有限寻址能力。

公开(公告)号：US4037215A

公开(公告)日：1977-07-19

申请号：US682222

申请日：1976-04-30

申请人： Richard Eugene Birney ,  Michael Ian Davis ,  Robert Allen Hood ,  Lynn Allan Graybiel ,  Samuel Kahn ,  William Steese Osborne

发明人： Richard Eugene Birney ,  Michael Ian Davis ,  Robert Allen Hood ,  Lynn Allan Graybiel ,  Samuel Kahn ,  William Steese Osborne

IPC分类号： G06F12/14 ,  G06F12/02 ,  G06F9/20

CPC分类号： G06F12/0292

摘要： Active address keys (AAK) are translated into respective addressabilities in physical main memory. Each addressability comprises one or more physical blocks which may be scattered in the main memory. Each address key represents the assigned addressability in main memory for a logical address space. Plural key register sections may be loaded with the same or different address keys. For each storage access request, received from a processor or I/O channel, AAK select circuits outgate to the translator the key in the key register section corresponding to the type of the current storage access request to determine the addressability available to the access request. Each address key identifies a particular stack of one or more segmentation registers. Each segmentation register can be assigned the address of any segment (i.e. a block of contiguous physical addresses located anywhere in the main memory). Each segmentation register also has validity and read-only flag bits for its assigned block. Each stack can translate a contiguous set of logical addresses into physical addresses. For each storage access request for a logical address, and not apparent to the usury program, a stack is addressed by the AAK to translate the logical address to a real address within the assigned addressability. Then a register in the stack is selected by high-order bits in the logical address. The addressed register outputs an assigned block address. Low order bits in the logical address select a byte address in the assigned block. The main memory can have any physical size, which is coordinated with the number of stacks, and to the number of segmentation registers in each stack.

摘要翻译： 活动地址键（AAK）被转换为物理主存储器中的相应地址。 每个可寻址性包括一个或多个可能分散在主存储器中的物理块。 每个地址密钥表示逻辑地址空间在主存储器中分配的可寻址性。 多个密钥寄存器部分可以被加载相同或不同的地址密钥。 对于从处理器或I / O通道接收的每个存储访问请求，AAK选择电路向翻译器输出与当前存储访问请求的类型相对应的密钥寄存器部分中的密钥，以确定可用于访问请求的可寻址性。 每个地址密钥标识一个或多个分段寄存器的特定堆栈。 可以为每个分段寄存器分配任何段的地址（即位于主存储器中任何地方的连续物理地址的块）。 每个分段寄存器还具有其分配块的有效性和只读标志位。 每个堆栈可以将一组连续的逻辑地址转换为物理地址。 对于逻辑地址的每个存储访问请求，并且对于高利率程序而言并不明显，由AAK寻址堆栈，以将逻辑地址转换为所分配的可寻址性内的真实地址。 然后，逻辑地址中的高位选择堆栈中的寄存器。 寻址的寄存器输出分配的块地址。 逻辑地址中的低位位选择分配块中的一个字节地址。 主存储器可以具有与堆栈数量协调的任何物理大小以及每个堆栈中的分段寄存器的数量。

公开(公告)号：US4042913A

公开(公告)日：1977-08-16

申请号：US681982

申请日：1976-04-30

申请人： Richard Eugene Birney ,  Michael Ian Davis ,  Lynn Allan Graybiel ,  Robert Allen Hood ,  Samuel Kahn ,  William Steese Osborne

发明人： Richard Eugene Birney ,  Michael Ian Davis ,  Lynn Allan Graybiel ,  Robert Allen Hood ,  Samuel Kahn ,  William Steese Osborne

IPC分类号： G06F9/312 ,  G06F11/00 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24 ,  G06F9/00

CPC分类号： G06F9/30043 ,  G06F12/1458 ,  G06F13/122

摘要： The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

摘要翻译： 本公开描述了用于将地址键值加载或存储在键控寄存器控制的寻址系统中的一个或多个地址密钥寄存器部分中的指令操作控制。 该控制装置将处理器中的地址键寄存器（AKR）的一个或所有关键寄存器部分加载或存储在主存储器或通用寄存器（GPR）中的字中。 加载或存储控制都以相同的指令格式操作，其中一个字段指示操作是否是指定的AKR部分的加载或存储。 另一个字段指定要加载或存储的一个AKR部分或所有AKR部分。 还有一个字段指定操作是从主存储器还是从主存储器或GPR。 本公开提供了利用微码操作以执行这些操作的电路。

公开(公告)号：US4037214A

公开(公告)日：1977-07-19

申请号：US681984

申请日：1976-04-30

申请人： Richard Eugene Birney ,  Michael Ian Davis ,  Robert Allen Hood

发明人： Richard Eugene Birney ,  Michael Ian Davis ,  Robert Allen Hood

IPC分类号： G06F11/00 ,  G06F12/00 ,  G06F12/06 ,  G06F12/14 ,  G06F15/16 ,  G06F15/177 ,  G06F21/24 ,  G06F13/00

CPC分类号： G06F12/1458 ,  G06F12/0623

摘要： A plurality of key register sections in a processor respectively associated with different machine-sensed types of accesses to a main storage of a computer system. A processor address key register (AKR) includes the following sections: (1) a section associated with an instruction-fetch type access, (2) a section associated with a source-operand fetch type access, and (3) a section associated with a sink-operand store/fetch type access. Other key register sections may be associated with respective sub-channel store/fetch type accesses. Circuits are provided which sense the different access types to select and outgate a key contained in the corresponding key register section.The values of the keys are associated with different addressabilities (i.e. address spaces). Each different key value is associated with a different stack of translation registers for containing the block addresses in real storage currently assigned to the respective addressabilities.Each key outgated from a respective register section selects an address space by selecting the associated stack of addressing registers to relocatably translate a logical address to a physical storage location within the address space selected by the outgated key.

摘要翻译： 处理器中的多个键寄存器部分分别与对计算机系统的主存储器的不同的机器感测类型的访问相关联。 处理器地址密钥寄存器（AKR）包括以下部分：（1）与指令获取类型访问相关的部分，（2）与源操作数获取类型访问相关联的部分，以及（3）与 一个sink操作数存储/获取类型访问。 其他关键寄存器部分可以与相应的子信道存储/获取类型访问相关联。 提供了检测不同访问类型以选择和打开包含在相应的密钥寄存器部分中的密钥的电路。

公开(公告)号：US4038645A

公开(公告)日：1977-07-26

申请号：US682224

申请日：1976-04-30

申请人： Richard Eugene Birney ,  Michael Ian Davis

发明人： Richard Eugene Birney ,  Michael Ian Davis

IPC分类号： G06F11/00 ,  G06F12/14 ,  G06F21/24 ,  G06F13/00

CPC分类号： G06F12/1458

摘要： Combines a storage protect key stack with an access key register (AKR) and active access key (AAK) select circuits. Storage key entries in the stack correspond to the physical blocks in main memory. This combination can provide storage protection for different storage access types within address sub-ranges in the main memory associated with respective access keys. The sub-ranges are blocks of addresses within the full range of addresses of the physical memory. The protect key operation applies to physical addresses, and it obtains system addressing compatibility with an address translation operation using the same access keys as address keys with program logical addresses.Special features include a shared protect key, which need not be loaded in the AKR, to make specified sub-range(s) shareable by all users of the system, so that any user can access the blocks in memory associated with the shared protect key. For I/O accesses, an override is provided which ignores any read-only control of any memory block to which an I/O access is requested. Supervisor accesses can be made in all key areas, regardless of the AAK, the protect keys, or the read-only flag bits.

公开(公告)号：US4103329A

公开(公告)日：1978-07-25

申请号：US755105

申请日：1976-12-28

申请人： Michael Ian Davis ,  Robert Allen Hood ,  Gary Wayne Mayes

发明人： Michael Ian Davis ,  Robert Allen Hood ,  Gary Wayne Mayes

IPC分类号： G06F9/305 ,  G06F9/34 ,  G06F12/04 ,  G06F9/06

CPC分类号： G06F12/04

摘要： Hardware facilities are described whereby the handling of data represented by variable length fields of bits may be made faster, use less storage and be less prone to errors in programming. The bit fields are handled independently of the natural storage addressing elements and boundaries. Data may be packed into main storage with the highest efficiency, and manipulated with a fast and efficient hardware instruction set.

公开(公告)号：US4038642A

公开(公告)日：1977-07-26

申请号：US682229

申请日：1976-04-30

申请人： Max Abbott Bouknecht ,  Michael Ian Davis ,  Louis Peter Vergari

发明人： Max Abbott Bouknecht ,  Michael Ian Davis ,  Louis Peter Vergari

IPC分类号： G06F3/00 ,  G06F13/26 ,  G06F13/34 ,  G06F3/04 ,  G06F13/00

CPC分类号： G06F13/26 ,  G06F13/34

摘要： The interface between I/O control logic, or channel, and peripheral devices permits simultaneous transfer of command, device address, and data, and includes logic in a peripheral device control unit for dynamic change of the attached peripheral device interrupt priority level while the device may be executing a prior command. The I/O control logic includes means for initiating serial poll signalling while other transfers are taking place on the interface.

公开(公告)号：US4047161A

公开(公告)日：1977-09-06

申请号：US681953

申请日：1976-04-30

申请人： Michael Ian Davis

发明人： Michael Ian Davis

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F9/19 ,  G06F9/20

CPC分类号： G06F9/4881 ,  G06F9/462

摘要： A data processing system is described which has multiple sets of registers each of which is capable of autonomously controlling a common storage and common arithmetic and logic control circuits to execute respective tasks of a program. Level status blocks (LSBs), each assigned to a respective task, are held in main storage; and each contains such address and status data as is required for task execution in a controlled environment. Apparatus, including a current level register, a selected level register, a pending level register and an in-process bit latch, is controlled during the execution of a load level status block (LLSB) instruction to transfer the LSB of a selected task from storage to the selected register set, determine the status of the in-process bit of the selected task LSB and the relative priority levels of the current and selected tasks, and pursuant to said two determinations handle the task dispatching, preemption, enqueuing, dequeuing functions without the need for further software processing. At the completion of the LLSB instruction execution, either the current task execution is continued, the selected task is initiated, a pending task is initiated or a system wait state is entered. A store level status block (STLSB) instruction is executed to copy the LSB of a selected task from the register set to storage. Hardware backup registers are provided to hold certain updated status of the current register set to improve performance. These backup registers are changed during the LLSB execution if task switching occurs and are restored to the current register set during STLSB execution.

摘要翻译： 描述了一种数据处理系统，其具有多组寄存器，每组寄存器能够自主地控制公共存储器和公共算术和逻辑控制电路以执行程序的相应任务。 每个分配给相应任务的级别状态块（LSB）保存在主存储器中; 并且每个都包含在受控环境中执行任务所需的这样的地址和状态数据。 在执行负载电平状态块（LLSB）指令期间控制包括电流电平寄存器，所选电平寄存器，未决电平寄存器和进程内位锁存器的装置，以将所选任务的LSB从存储器 到所选择的寄存器集合，确定所选任务LSB的进程内位置的状态以及当前和所选任务的相对优先级，并且根据所述两个确定来处理任务调度，抢占，排队，出队功能而没有 需要进一步的软件处理。 在完成LLSB指令执行时，当前任务执行继续，所选任务被启动，未决任务被启动或者系统等待状态被输入。 执行存储级状态块（STLSB）指令，将所选任务的LSB从寄存器集复制到存储。 提供硬件备份寄存器以保持当前寄存器集的某些更新状态，以提高性能。 如果任务切换发生，这些备份寄存器在LLSB执行期间发生更改，并在STLSB执行期间恢复到当前寄存器集。

公开(公告)号：US4041462A

公开(公告)日：1977-08-09

申请号：US682002

申请日：1976-04-30

申请人： Michael Ian Davis ,  Gary Wayne Mayes ,  Thomas Stephen McDermott ,  Larry Edward Wise

发明人： Michael Ian Davis ,  Gary Wayne Mayes ,  Thomas Stephen McDermott ,  Larry Edward Wise

IPC分类号： G06F9/40 ,  G06F9/42 ,  G06F9/18

CPC分类号： G06F9/4426 ,  G06F9/4425

摘要： A data processing system is described wherein, during linkage to a subroutine, by a single machine instruction, a complete status save and the assignment of a dynamic work area are effected. By another single machine instruction the process is reversed. The elements of the complete machine status and the dynamic work area are retained in a hardware controlled stack, thus permitting nesting of the subroutine calls.

摘要翻译： 描述了一种数据处理系统，其中在通过单个机器指令连接到子程序期间，实现完整的状态保存和动态工作区的分配。 通过另一个单机指令，该过程相反。 完整的机器状态和动态工作区域的元素保留在硬件控制的堆栈中，从而允许嵌套子程序调用。