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1.发明授权Method and apparatus for invalidating entries within a translation control entry (TCE) cache 有权用于使翻译控制条目（TCE）高速缓存中的条目无效的方法和装置公开(公告)号：US07308557B2
公开(公告)日：2007-12-11
申请号：US11054182
申请日：2005-02-09
CPC分类号： G06F12/0837 , G06F12/084 , G06F12/1081 , G06F2212/1041 , G06F2212/683
摘要： A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The host bridge includes a TCE cache. The TCE cache contains the most-recently use copies of TCEs in a TCE table located in a system memory. In response to a modification to a TCE in the TCE table by one of the processors, a memory mapped input/output (MMIO) Store is sent to a TCE invalidate register to specify an address of the modified TCE. The data within the TCE invalidate register is then utilized to generate a command for invalidating an entry in the TCE cache containing an unmodified copy of the modified TCE in the TCE table. The command is subsequently sent to the host bridge to invalidate the entry in the TCE cache.
摘要翻译： 公开了一种使翻译控制条目（TCE）高速缓存内的条目无效的方法和装置。 主机桥耦合在一组处理器和一组适配器之间。 主机桥包括TCE缓存。 TCE缓存包含位于系统内存中的TCE表中最近使用的TCE的副本。 响应于一个处理器对TCE表中的TCE进行修改，将存储器映射的输入/输出（MMIO）存储发送到TCE无效寄存器，以指定修改的TCE的地址。 然后使用TCE无效寄存器内的数据来产生用于使包含TCE表中修改的TCE的未修改副本的TCE缓存中的条目无效的命令。 该命令随后发送到主机桥，使TCE缓存中的条目无效。
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2.发明授权Method and system for interfacing components of a computing system with a pair of unidirectional, point-to-point buses 失效用于将计算系统的组件与一对单向点对点总线接口的方法和系统公开(公告)号：US07568060B2
公开(公告)日：2009-07-28
申请号：US11304474
申请日：2005-12-15
申请人： George W. Daly, Jr. , James S. Fields, Jr. , Donald G. Grice , Thomas J. Heller , Appoloniel N. Tankeh
发明人： George W. Daly, Jr. , James S. Fields, Jr. , Donald G. Grice , Thomas J. Heller , Appoloniel N. Tankeh
CPC分类号： G06F13/4269
摘要： A method of interfacing two components of a computing system is provided wherein the method includes providing a pair of unidirectional, point-to-point buses to transmit data between a master bus controller of the computing system and a slave bus controller of a processor unit of the computing system. The method also includes providing means for transmitting a command packet with an address associated with data pertaining to the command from the master bus controller to the slave bus controller. In addition, the method includes providing means for determining by the slave bus controller whether the slave bus controller can accept the command. The method further includes providing means for transmitting an acknowledgement from the slave bus controller to the master bus controller after the slave bus controller receives a first signaling interval for the command packet if the slave bus controller can accept the command packet.
摘要翻译： 提供了一种接口计算系统的两个组件的方法，其中所述方法包括提供一对单向点对点总线以在所述计算系统的主总线控制器与所述计算系统的总线控制器之间传送数据， 计算系统。 该方法还包括提供用于发送具有与从主总线控制器到从总线控制器的命令有关的数据相关联的地址的命令分组的装置。 此外，该方法包括提供用于由从总线控制器确定从总线控制器是否可以接受命令的装置。 该方法还包括：如果从总线控制器可以接收命令包，则在从总线控制器接收到命令分组的第一信令间隔之后，提供用于在从总线控制器向主总线控制器发送确认的装置。
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3.发明授权Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes 失效允许I / O写入操作和多个操作范围的流水线的数据处理系统和方法公开(公告)号：US07725619B2
公开(公告)日：2010-05-25
申请号：US11226967
申请日：2005-09-15
申请人： George W. Daly, Jr. , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
发明人： George W. Daly, Jr. , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.
摘要翻译： 数据处理系统至少包括具有输入/输出（I / O）控制器的第一处理节点和包括用于存储器的存储器控制器的第二处理。 存储器控制器按顺序从I / O控制器接收流水线的第一和第二DMA写入操作，其中第一和第二DMA写操作分别针对第一和第二地址。 响应于第二DMA写入操作，存储器控制器建立与第二地址相关联的域指示符的状态，以指示包括第一处理节点的操作范围。 响应于所述存储器控制器接收到指定所述第二地址并且具有排除所述第一处理节点的范围的数据访问请求，所述存储器控制器基于所述第一处理节点的状态强迫所述数据访问请求被重新发布，所述范围包括所述第一处理节点 与第二个地址关联的域指示符。
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4.发明授权Method for interfacing components of a computing system with a pair of unidirectional, point-to-point buses 失效用于将计算系统的组件与一对单向点对点总线接口的方法公开(公告)号：US07562171B2
公开(公告)日：2009-07-14
申请号：US11854004
申请日：2007-09-12
申请人： George W. Daly, Jr. , James S. Fields, Jr. , Donald G. Grice , Thomas K. Heller, Jr. , Appoloniel N. Tankeh
发明人： George W. Daly, Jr. , James S. Fields, Jr. , Donald G. Grice , Thomas K. Heller, Jr. , Appoloniel N. Tankeh
CPC分类号： G06F13/4269
摘要： A method of interfacing two components of a computing system is provided wherein the method includes providing a pair of unidirectional, point-to-point buses to transmit data between a master bus controller of the computing system and a slave bus controller of a processor unit of the computing system. The method also includes providing means for transmitting a command packet with an address associated with data pertaining to the command from the master bus controller to the slave bus controller. In addition, the method includes providing means for determining by the slave bus controller whether the slave bus controller can accept the command. The method further includes providing means for transmitting an acknowledgement from the slave bus controller to the master bus controller after the slave bus controller receives a first signaling interval for the command packet if the slave bus controller can accept the command packet.
摘要翻译： 提供了一种接口计算系统的两个组件的方法，其中所述方法包括提供一对单向点对点总线以在所述计算系统的主总线控制器与所述计算系统的总线控制器之间传送数据， 计算系统。 该方法还包括提供用于发送具有与从主总线控制器到从总线控制器的命令有关的数据相关联的地址的命令分组的装置。 此外，该方法包括提供用于由从总线控制器确定从总线控制器是否可以接受命令的装置。 该方法还包括提供用于在从总线控制器接收到命令分组之后从属总线控制器接收到用于命令分组的第一信令间隔的从总线控制器向主总线控制器发送确认的装置。
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5.发明授权Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations 失效在直接存储器访问（DMA）写入操作期间使高速缓存线无效的方法和装置公开(公告)号：US07788423B2
公开(公告)日：2010-08-31
申请号：US12187094
申请日：2008-08-06
IPC分类号： G06F13/00
CPC分类号： G06F12/0835 , G06F13/28
摘要： A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.
摘要翻译： 公开了一种在直接存储器访问（DMA）写入操作期间使高速缓存线无效的方法和装置。 最初，外围设备发出多高速缓存行DMA请求。 多高速缓存行DMA请求被缓存内存窥探。 然后确定高速缓冲存储器是否包括存储在多高速缓存行DMA请求所针对的系统存储单元中的数据的副本。 响应于确定高速缓冲存储器包括存储在多高速缓存行DMA请求所针对的系统存储器位置中的数据的副本，高速缓冲存储器内的多个高速缓存行连续无效。
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6.发明授权Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations 失效在直接存储器访问（DMA）写入操作期间使高速缓存线无效的方法和装置公开(公告)号：US07451248B2
公开(公告)日：2008-11-11
申请号：US11054183
申请日：2005-02-09
IPC分类号： G06F13/28
CPC分类号： G06F12/0835 , G06F13/28
摘要： A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.
摘要翻译： 公开了一种在直接存储器访问（DMA）写入操作期间使高速缓存线无效的方法和装置。 最初，外围设备发出多高速缓存行DMA请求。 多高速缓存行DMA请求被缓存内存窥探。 然后确定高速缓冲存储器是否包括存储在多高速缓存行DMA请求所针对的系统存储单元中的数据的副本。 响应于确定高速缓冲存储器包括存储在多高速缓存行DMA请求所针对的系统存储器位置中的数据的副本，高速缓冲存储器内的多个高速缓存行连续无效。
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7.发明授权Data processing system and method of communication that reduce latency of write transactions subject to retry 失效数据处理系统和通信方法，可减少写入事务的延迟，重试公开(公告)号：US06687795B2
公开(公告)日：2004-02-03
申请号：US09742763
申请日：2000-12-20
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A data processing system includes a plurality of snoopers coupled to an interconnect. In response to a memory access request transmitted on an interconnect by one of the snoopers receiving a Retry response, a determination is made whether or not the Retry response was caused by a target snooper that will service the memory access request. If not, the target snooper services the memory access request in spite of the Retry response. In a preferred embodiment in which the memory access request is a write request and the target snooper is a memory controller, stale data cached by at least one snooper in association with the address are also invalidated by a snooper, such as the memory controller, transmitting at least one address-only kill transaction on the interconnect. Advantageously, the address-only kill transaction can be issued concurrently with or following servicing the write request so that the write request does not incur latency by waiting until all stale copies of the data have been invalidated.
摘要翻译： 数据处理系统包括耦合到互连的多个窥探器。 响应于由接收到重试响应的窥探者之一在互连上发送的存储器访问请求，确定重试响应是否由将服务于存储器访问请求的目标侦听器引起。 如果不是，目标侦听器服务于内存访问请求，尽管有重试响应。 在其中存储器访问请求是写请求并且目标窥探者是存储器控制器的优选实施例中，由地址相关联的至少一个窥探者缓存的陈旧数据也被诸如存储器控制器之类的窥探者无效 互连上至少有一个仅地址杀死事务。 有利的是，仅针对地址的中断事务可以与服务于写入请求同时发送或者在服务写入请求之后发出，从而通过等待数据的所有陈旧副本已经被无效，写入请求不会引起等待时间。
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