-
公开(公告)号：US06523140B1
公开(公告)日：2003-02-18
申请号：US09414337
申请日：1999-10-07
IPC分类号： H02H305
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/0793
摘要： A method and implementing computer system is provided in which specific device identification information is acquired when a faulty condition is detected during an information transfer transaction, and the condition is reported to the device driver of the identified device for corrective action without initiating a system shut-down. In one example, PCI adapter sequence information, including tag number, requester bus number, requester device number and requester function number is captured and used in reporting an error condition in order to identify and isolate the adapter in a recovery operation.
摘要翻译： 提供了一种方法和实现的计算机系统，其中在信息传输交易期间检测到故障状况时获取特定的设备识别信息，并且将该条件报告给所识别的设备的设备驱动程序以进行纠正，而不启动系统关闭， 下。 在一个示例中，捕获PCI适配器序列信息，包括标签号，请求者总线号，请求者设备号和请求者功能号，并用于报告错误状况，以便在恢复操作中识别和隔离适配器。
-
2.发明授权DMA windowing in an LPAR environment using device arbitration level to allow multiple IOAs per terminal bridge 有权使用设备仲裁级别在LPAR环境中DMA窗口，以允许每个终端桥接多个IOA公开(公告)号：US06823404B2
公开(公告)日：2004-11-23
申请号：US09766764
申请日：2001-01-23
IPC分类号： G06F300
CPC分类号： G06F13/28
摘要： A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned data processing system, from fetching or corrupting data from a memory location allocated to another OS image within the data processing system is provided. A hypervisor prevents transmission of data between an input/output adapter in one of the logical partitions and memory locations assigned to other logical partitions during a direct memory access (DMA) operation by assigning each of the input/output adapters a range of I/O bus DMA addresses. The I/O adapters (IOAs) are connected to PCI host bridges via terminal bridges. A single terminal bridge may support multiple IOAs, in which case every terminal bridge has a plurality of sets of range registers, each associated with a respective one of the IOAs to which it is connected. An arbiter is provided which selects one of the input/output adapters to use the PCI bus. The terminal bridge can examine the grant signals from the arbiter to the IOAs, to determine which set of range registers is to be used.
摘要翻译： 用于防止在逻辑分区的数据处理系统中由操作系统（OS）映像使用的输入/输出（I / O）适配器的方法，系统和装置从分配给另一个OS映像的存储器位置获取或破坏数据 在数据处理系统内提供。 虚拟机管理程序防止在直接存储器访问（DMA）操作期间通过分配每个输入/输出适配器一个I / O范围的逻辑分区之一和分配给其他逻辑分区的存储器位置之间的输入/输出适配器之间的数据传输 总线DMA地址。 I / O适配器（IOA）通过终端桥连接到PCI主机桥。 单个终端桥可以支持多个IOA，在这种情况下，每个终端桥具有多组范围寄存器，每个范围寄存器与其所连接的IOA中的相应一个相关联。 提供了一个仲裁器，其选择一个输入/输出适配器来使用PCI总线。 终端桥可以检查从仲裁器到IOA的授权信号，以确定要使用哪个范围寄存器组。
-
公开(公告)号：US06973510B2
公开(公告)日：2005-12-06
申请号：US10953920
申请日：2004-09-29
CPC分类号： G06F13/28
摘要： A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned data processing system, from fetching or corrupting data from a memory location allocated to another OS image within the data processing system is provided. A hypervisor prevents transmission of data between an input/output adapter in one of the logical partitions and memory locations assigned to other logical partitions during a direct memory access (DMA) operation by assigning each of the input/output adapters a range of I/O bus DMA addresses. The I/O adapters (IOAs) are connected to PCI host bridges via terminal bridges. A single terminal bridge may support multiple IOAs, in which case every terminal bridge has a plurality of sets of range registers, each associated with a respective one of the IOAs to which it is connected. An arbiter is provided which selects one of the input/output adapters to use the PCI bus. The terminal bridge can examine the grant signals from the arbiter to the IOAs, to determine which set of range registers is to be used.
-
4.发明授权Method and system for interrupt handling using device pipelined packet transfers 失效使用设备流水线分组传输的中断处理方法和系统公开(公告)号：US06493779B1
公开(公告)日：2002-12-10
申请号：US09224111
申请日：1998-12-21
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.
摘要翻译： 提供了一种实现流水线分组传输（PPT）的方法和装置。 PPT方法包括请求阶段和响应阶段。 PPT请求阶段涉及PPT请求主机，向PPT请求目标传送要求的中断的源地址，目的地地址和信息分组。 PPT响应阶段涉及PPT请求目标成为PPT响应主机，PPT响应主机向PPT请求主机传递目的地地址和包括中断处理信息的数据分组。 流水线分组传输（PPT）根据预定的处理优先级进行排序，以提高性能并避免死锁。
-
5.发明授权Method and system for interrupt handling using system pipelined packet transfers 失效使用系统流水线分组传输的中断处理方法和系统公开(公告)号：US06418497B1
公开(公告)日：2002-07-09
申请号：US09224119
申请日：1998-12-21
IPC分类号： G06F948
CPC分类号： G06F13/26
摘要： A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.
摘要翻译： 提供了一种实现流水线分组传输（PPT）的方法和装置。 PPT方法包括请求阶段和响应阶段。 PPT请求阶段涉及PPT请求主机，向PPT请求目标传送要求的中断的源地址，目的地地址和信息分组。 PPT响应阶段涉及PPT请求目标成为PPT响应主机，PPT响应主机向PPT请求主机传递目的地地址和包括中断处理信息的数据分组。 流水线分组传输（PPT）根据预定的处理优先级进行排序，以提高性能并避免死锁。
-
6.发明授权Associating buffers in a bus bridge with corresponding peripheral devices to facilitate transaction merging 失效将总线桥中的缓冲区与对应的外围设备相关联，以便于事务合并公开(公告)号：US06324612B1
公开(公告)日：2001-11-27
申请号：US09210133
申请日：1998-12-10
IPC分类号： G06F1340
CPC分类号： G06F13/4059 , G06F13/4031
摘要： A bus bridge including a buffer pool and steering logic where the buffer pool is organized as a plurality of buffers sets including at least first and second buffer sets and the steering logic is adapted to store transactions originating with a first peripheral device in the first buffer set and transactions originating with a second peripheral device in the second buffer set. Transactions may arrive via a secondary bus, such as a PCI bus, coupled to the bus bridge. The bridge further allows relaxed transaction ordering rules compared to conventional PCI transaction ordering rules by identifying transactions by grant signals and thus allows steering of transactions from the first and second devices to first and second buffer sets respectively. The bridge is suitably adapted for combining or merging two or more transactions within each buffer set. Each buffer set preferably includes one or more buffers for temporarily storing transactions arriving from the secondary bus and bound for a primary bus. The primary bus may comprise a host bus connected to one or more processors or an additional PCI bus or other peripheral bus. The invention further contemplates a computer system including at least one processor, a bridge coupled to the processor via a host bus, and a plurality of peripheral devices including first and second peripheral devices coupled to the bridge via a secondary bus. In one embodiment, the bridge is configured to receive first and second request signals from the first and second peripheral devices respectively. The bridge preferably further includes arbitration logic for arbitrating mastership of the secondary bus in response to the request signals to produce first and second grant signals. The steering logic is suitably configured to utilize the first and second grant signals to determine the source of a subsequent transaction.
摘要翻译： 一种包括缓冲池和转向逻辑的总线桥，其中所述缓冲池被组织为包括至少第一和第二缓冲器组的多个缓冲器组，并且所述转向逻辑适于将始发于第一外围设备的事务存储在所述第一缓冲器组中 以及在第二缓冲器组中产生具有第二外围设备的交易。 事务可以通过耦合到总线桥的辅助总线（诸如PCI总线）到达。 与传统PCI事务排序规则相比，通过由授权信号识别事务并且因此允许将事务从第一和第二设备分别转向第一和第二缓冲器组，桥还允许轻松的事务排序规则。 该桥适用于组合或合并每个缓冲区内的两个或多个事务。 每个缓冲器组优选地包括一个或多个缓冲器，用于临时存储从次级总线到达并且被绑定到主总线的事务。 主总线可以包括连接到一个或多个处理器或附加PCI总线或其他外围总线的主机总线。 本发明进一步考虑了一种包括至少一个处理器，经由主机总线耦合到处理器的桥的计算机系统，以及包括通过次级总线耦合到桥接器的第一和第二外围设备的多个外围设备。 在一个实施例中，桥被配置为分别从第一和第二外围设备接收第一和第二请求信号。 桥接器优选地还包括用于响应于请求信号来仲裁辅助总线的主管以产生第一和第二授权信号的仲裁逻辑。 转向逻辑被适当地配置为利用第一和第二授权信号来确定后续交易的来源。
-
公开(公告)号：US06301630B1
公开(公告)日：2001-10-09
申请号：US09210127
申请日：1998-12-10
IPC分类号： G06F1300
CPC分类号： G06F13/4059
摘要： A bus bridge including a buffer pool comprised of a first and a second buffer sets. The first and second buffer sets are associated with first and second peripheral devices respectively. The bridge is configured to receive an interrupt and identify the interrupt source. A buffer set associated with the interrupt source is selected and transactions in the selected buffer set flushed prior to forwarding the interrupt to a processor. The bridge is preferably configured to identify the interrupt source by receiving a first interrupt signal from the first peripheral device and a second interrupt signal from the second peripheral device. Preferably, the bridge is configured to flush the transactions by pushing them into system memory via a primary bus such as a host bus of a processor. The invention further contemplates a system including a processor coupled to a host bus, a system memory, a bus bridge as described coupled between the host bus and a secondary bus, and first and second peripheral devices coupled to the secondary bus. Upon receiving an interrupt, the bridge is configured to identify the interrupt source, select a buffer set associated with the interrupt source, and flush posted memory write transactions in the selected buffer set, all prior to forwarding the interrupt to the processor. In one embodiment, the bridge, the first and second peripheral devices, and the secondary bus are compliant with the PCI specification. The bridge is configured in one embodiment to receive unique first and second interrupt signals from the first and second peripheral devices respectively.
摘要翻译： 包括由第一和第二缓冲器组构成的缓冲池的总线桥。 第一和第二缓冲器组分别与第一和第二外围设备相关联。 桥接器配置为接收中断并识别中断源。 选择与中断源关联的缓冲区，并将所选缓冲区中的事务刷新，然后再将中断转发给处理器。 优选地，桥被配置为通过从第一外围设备接收第一中断信号和来自第二外围设备的第二中断信号来识别中断源。 优选地，桥被配置为通过经由诸如处理器的主机总线的主总线将其推入系统存储器来刷新事务。 本发明进一步考虑了一种系统，其包括耦合到主机总线的处理器，系统存储器，耦合在主机总线和辅助总线之间的总线桥，以及耦合到次级总线的第一和第二外围设备。 在接收到中断时，桥被配置为识别中断源，选择与中断源相关联的缓冲区集合，以及在将中断转发到处理器之前清除所选缓冲区中的已发布的存储器写入事务。 在一个实施例中，桥接器，第一和第二外围器件以及辅助总线符合PCI规范。 在一个实施例中，桥被配置为分别从第一和第二外围设备接收唯一的第一和第二中断信号。
-
8.发明授权Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across a PCI host bridge supporting multiple PCI buses 失效支持通过支持多个PCI总线的PCI主机桥的外围组件互连（PCI）对等访问的方法和系统公开(公告)号：US06182178B2
公开(公告)日：2001-01-30
申请号：US09106953
申请日：1998-06-30
IPC分类号： G06F1338
CPC分类号： G06F13/4045
摘要： A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. First and second PCI local buses are connected to the system bus through a PCI host bridge. The first and second PCI local buses have sets of in-line electronic switches, dividing the PCI local buses into PCI local bus segments supporting a plurality of PCI peripheral component slots for connecting PCI devices. The sets of in-line electronic switches are open and closed in accordance with bus control logic within the PCI host bridge allowing up to fourteen or more PCI peripheral component slots for connecting up to fourteen PCI devices to have access through a single PCI host bridge to the system bus. An internal PCI-to-PCI bridge is provided to allow a PCI device to share data with another PCI device as peer-to-peer devices across the first and second PCI local bus segments.
摘要翻译： 公开了一种通过在数据处理系统内具有多个PCI接口的单个PCI主机桥来支持多个外围组件互连（PCI）局部总线的方法和系统。 根据本发明的方法和系统，处理器和系统存储器连接到系统总线。 第一和第二PCI本地总线通过PCI主机桥连接到系统总线。 第一和第二PCI本地总线具有一组在线电子开关，将PCI本地总线划分成支持用于连接PCI设备的多个PCI外围组件插槽的PCI本地总线段。 根据PCI主机桥中的总线控制逻辑，这些在线电子开关是打开和关闭的，允许多达十四个或更多个PCI外设组件插槽，用于连接多达十四个PCI设备，以通过单个PCI主机桥访问 系统总线。 提供内部PCI至PCI桥接器，以允许PCI设备与第一和第二PCI本地总线段之间的对等设备与另一PCI设备共享数据。
-
9.发明授权Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data-processing system 失效支持数据处理系统内多个PCI主机桥的外围组件互连（PCI）对等访问的方法和系统
公开(公告)号：US5761462A
公开(公告)日：1998-06-02
申请号：US766736
申请日：1996-12-13
CPC分类号： G06F13/4027
摘要： A method for supporting peer-to-peer access across separate Peripheral Component Interconnect (PCI) host bridges within a data-processing system is described. In accordance with the method and system of the present invention, during an access request from a PCI device, a first determination is made as to whether or not the access request is for a system memory attached to a system bus. In response to a determination that the access request is not for a system memory attached to the system bus, another determination is made as to whether or not the access request is for a PCI device under the same PCI host bridge as the requesting PCI device. In response to a determination that the access request is not for a PCI device under the same PCI host bridge as the requesting PCI device, executing added protocols for the support of PCI peer-to-peer access request across separate PCI host bridges within the data-processing system.
摘要翻译： 描述了一种支持数据处理系统内单独的外围组件互连（PCI）主机桥的对等访问的方法。 根据本发明的方法和系统，在来自PCI设备的访问请求期间，首先确定访问请求是否用于连接到系统总线的系统存储器。 响应于确定访问请求不是连接到系统总线的系统存储器，则另外确定访问请求是否用于与请求的PCI设备相同的PCI主机桥下的PCI设备。 响应于确定访问请求不适用于与请求的PCI设备相同的PCI主机桥下的PCI设备，在数据中的单独PCI主机桥上执行用于支持PCI对等访问请求的附加协议 处理系统。
-
10.发明授权Method and apparatus for reporting unauthorized attempts to access nodes in a network computing system 有权用于报告未经授权的访问网络计算系统中的节点的尝试的方法和装置公开(公告)号：US07113995B1
公开(公告)日：2006-09-26
申请号：US09692348
申请日：2000-10-19
申请人： Bruce Leroy Beukema , Danny Marvin Neal , Gregory Francis Pfister , Renato John Recio , Steven Mark Thurber
发明人： Bruce Leroy Beukema , Danny Marvin Neal , Gregory Francis Pfister , Renato John Recio , Steven Mark Thurber
IPC分类号： G06F15/16
摘要： A method in a node for managing authorized attempts to access the node. A packet is received from a source, wherein the packet includes a first key. A determination is made as to whether the first key matches a second key for the node. The packet is dropped without a response to the source if the first key does not match the second key. Information from the packet is stored in response to this absence of a match. The information is sent to a selected recipient in response to a selected event, which may be, for example, either immediately or in response to polling to see if the information is present.
摘要翻译： 用于管理访问节点的授权尝试的节点中的方法。 从源接收分组，其中分组包括第一密钥。 确定第一个密钥是否与节点的第二个密钥相匹配。 如果第一个密钥与第二个密钥不匹配，数据包将被丢弃而不对源进行响应。 来自数据包的信息被存储以响应于缺少匹配。 响应于所选择的事件将信息发送到所选择的接收者，所选择的事件可以是例如立即地或响应于轮询来查看信息是否存在。
-
-
-
-
-
-
-
-
-
搜索结果
80 条记录 (耗时 0.032 秒)
