Dual inverter with common control

    公开(公告)号:US11575330B1

    公开(公告)日:2023-02-07

    申请号:US17388913

    申请日:2021-07-29

    摘要: An illustrative dual power inverter module includes a DC link capacitor electrically connectable to a source of high voltage direct current (DC) electrical power. A first power inverter is electrically connectable to the DC link capacitor and configured to convert high voltage DC electrical power to three phase high voltage alternating current (AC) electrical power and is configured to supply the three phase high voltage AC electrical power to a first electric motor. A second power inverter is electrically connectable to the DC link capacitor and configured to convert high voltage DC electrical power to three phase high voltage AC electrical power and is configured to supply the three phase high voltage AC electrical power to a second electric motor. A common controller is electrically connectable to the first power inverter and the second power inverter. The common controller is configured to control the first power inverter and the second power inverter.

    Dual Inverter with Common Control

    公开(公告)号:US20230032091A1

    公开(公告)日:2023-02-02

    申请号:US17388913

    申请日:2021-07-29

    摘要: An illustrative dual power inverter module includes a DC link capacitor electrically connectable to a source of high voltage direct current (DC) electrical power. A first power inverter is electrically connectable to the DC link capacitor and configured to convert high voltage DC electrical power to three phase high voltage alternating current (AC) electrical power and is configured to supply the three phase high voltage AC electrical power to a first electric motor. A second power inverter is electrically connectable to the DC link capacitor and configured to convert high voltage DC electrical power to three phase high voltage AC electrical power and is configured to supply the three phase high voltage AC electrical power to a second electric motor. A common controller is electrically connectable to the first power inverter and the second power inverter. The common controller is configured to control the first power inverter and the second power inverter.

    PULSE WIDTH MODULATION CLOCK SYNCHRONIZATION

    公开(公告)号:US20230070157A1

    公开(公告)日:2023-03-09

    申请号:US17987939

    申请日:2022-11-16

    IPC分类号: H02P27/08 H02M1/00 H02M7/5395

    摘要: A controller includes a first processor for a first power inverter. Computer-readable media is configured to store computer-executable instructions configured to cause the first processor to: generate a first clock signal and a second clock signal; identify a pulse width modulation method of the first power inverter and a pulse width modulation method of a second power inverter; identify and compare a switching frequency of the first power inverter and a switching frequency of the second power inverter; determine an optimized phase shift between the first power inverter and the second power inverter responsive to the pulse width modulation method of the first power inverter and the pulse width modulation method of the second power inverter and the switching frequency of the first power inverter and the switching frequency of the second power inverter; and synchronize the optimized phase shift between the first power inverter and the second power inverter. A second processor for the second power inverter is configured to receive the second clock signal.

    Pulse width modulation clock synchronization

    公开(公告)号:US11722089B2

    公开(公告)日:2023-08-08

    申请号:US17987939

    申请日:2022-11-16

    摘要: A controller includes a first processor for a first power inverter. Computer-readable media is configured to store computer-executable instructions configured to cause the first processor to: generate a first clock signal and a second clock signal; identify a pulse width modulation method of the first power inverter and a pulse width modulation method of a second power inverter; identify and compare a switching frequency of the first power inverter and a switching frequency of the second power inverter; determine an optimized phase shift between the first power inverter and the second power inverter responsive to the pulse width modulation method of the first power inverter and the pulse width modulation method of the second power inverter and the switching frequency of the first power inverter and the switching frequency of the second power inverter; and synchronize the optimized phase shift between the first power inverter and the second power inverter. A second processor for the second power inverter is configured to receive the second clock signal.

    TORQUE-EQUALIZING FAULT RESPONSE FOR ELECTRIC VEHICLE

    公开(公告)号:US20230031958A1

    公开(公告)日:2023-02-02

    申请号:US17389058

    申请日:2021-07-29

    IPC分类号: B60L3/00 B60L50/51

    摘要: Various disclosed embodiments include illustrative controllers, dual power inverter modules, and electric vehicles. In an illustrative embodiment, a controller includes one or more processors associated with a first and second power inverter for the drive unit. Computer-readable media for the one or more processors are each configured to store computer-executable instructions configured to cause the one or more processors to apply a same fault action to the first power inverter and the second power inverter responsive to a fault associated with an inverter chosen from the first power inverter and the second power inverter, wherein the same fault action includes applying equalized torque to each axle operatively coupled to the drive unit.

    Pulse width modulation clock synchronization

    公开(公告)号:US11533013B1

    公开(公告)日:2022-12-20

    申请号:US17388984

    申请日:2021-07-29

    摘要: Various disclosed embodiments include illustrative controllers, dual power inverter modules, and electric vehicles. In an illustrative embodiment, a controller includes a first processor for a first power inverter. Computer-readable media is configured to store computer-executable instructions configured to cause the first processor to: generate a first clock signal and a second clock signal; identify a pulse width modulation method of the first power inverter and a pulse width modulation method of a second power inverter; identify and compare a switching frequency of the first power inverter and a switching frequency of the second power inverter; determine an optimized phase shift between the first power inverter and the second power inverter responsive to the pulse width modulation method of the first power inverter and the pulse width modulation method of the second power inverter and the switching frequency of the first power inverter and the switching frequency of the second power inverter; and synchronize the optimized phase shift between the first power inverter and the second power inverter. A second processor for the second power inverter is configured to receive the second clock signal.