公开(公告)号：US20120278528A1

公开(公告)日：2012-11-01

申请号：US13096222

申请日：2011-04-28

申请人： Robert E. Galbraith ,  Murali N. Iyer ,  Timothy J. Larson ,  Steven P. Norgaard

发明人： Robert E. Galbraith ,  Murali N. Iyer ,  Timothy J. Larson ,  Steven P. Norgaard

IPC分类号： G06F12/02

CPC分类号： G06F12/0866 ,  G06F12/0804 ,  G06F2212/202 ,  Y02D10/13

摘要： A method and controller for implementing enhanced flash backed dynamic random access memory (DRAM) management, and a design structure on which the subject controller circuit resides are provided. An input/output adapter (IOA) includes at least one super capacitor, a data store (DS) dynamic random access memory (DRAM), a flash memory, a non-volatile random access memory (NVRAM), and a flash backed DRAM controller. Responsive to an adapter reset, Data Store DRAM testing including restoring a DRAM image from Flash to DRAM and testing of DRAM is performed. Mirroring of RAID configuration data and RAID parity update footprints between the NVRAM and DRAM is performed. Save of DRAM contents to the flash memory is controllably enabled when super capacitors have been sufficiently recharged and the flash memory erased.

摘要翻译： 一种用于实现增强型闪存备份动态随机存取存储器（DRAM）管理的方法和控制器，以及提供了主题控制器电路所在的设计结构。 输入/输出适配器（IOA）包括至少一个超级电容器，数据存储器（DS）动态随机存取存储器（DRAM），闪速存储器，非易失性随机存取存储器（NVRAM）和闪存的DRAM控制器 。 响应于适配器复位，数据存储DRAM测试包括将DRAM图像从Flash恢复到DRAM和测试DRAM。 执行RAID配置数据的镜像和NVRAM与DRAM之间的RAID奇偶校验更新覆盖。 当超级电容器被充分充电并且闪存被擦除时，将DRAM内容保存到闪速存储器是可控制的。

公开(公告)号：US20130046930A1

公开(公告)日：2013-02-21

申请号：US13606932

申请日：2012-09-07

申请人： Evangelos S. Eleftheriou ,  Robert Galbraith ,  Adrian C. Gerhard ,  Robert Haas ,  Xiao-Yu Hu ,  Murali N. Iyer ,  Ioannis Koltsidas ,  Timothy J. Larson ,  Steven P. Norgaard ,  Roman Pletka

发明人： Evangelos S. Eleftheriou ,  Robert Galbraith ,  Adrian C. Gerhard ,  Robert Haas ,  Xiao-Yu Hu ,  Murali N. Iyer ,  Ioannis Koltsidas ,  Timothy J. Larson ,  Steven P. Norgaard ,  Roman Pletka

IPC分类号： G06F12/08

CPC分类号： G06F11/1076 ,  G06F3/061 ,  G06F3/0662 ,  G06F3/0685

摘要： A method for optimizing locations of physical data accessed by one or more client applications interacting with a storage system, with the storage system comprising at least two redundancy groups having physical memory spaces and data bands. Each of the data bands corresponds to physical data stored on several of the physical memory spaces. A virtualized logical address space includes client data addresses utilizable by the one or more client applications. A storage controller is configured to map the client data addresses onto the data bands, such that a mapping is obtained, wherein the one or more client applications can access physical data corresponding to the data bands.

摘要翻译： 一种用于优化由与存储系统交互的一个或多个客户端应用访问的物理数据的位置的方法，其中所述存储系统包括具有物理存储器空间和数据带的至少两个冗余组。 每个数据带对应于存储在几个物理存储器空间上的物理数据。 虚拟化逻辑地址空间包括由一个或多个客户端应用程序可使用的客户机数据地址。 存储控制器被配置为将客户端数据地址映射到数据带上，使得获得映射，其中一个或多个客户端应用可以访问对应于数据带的物理数据。

公开(公告)号：US08667219B2

公开(公告)日：2014-03-04

申请号：US13606932

申请日：2012-09-07

申请人： Evangelos S. Eleftheriou ,  Robert Galbraith ,  Adrian C. Gerhard ,  Robert Haas ,  Xiao-Yu Hu ,  Murali N. Iyer ,  Ioannis Koltsidas ,  Timothy J. Larson ,  Steven P. Norgaard ,  Roman Pletka

发明人： Evangelos S. Eleftheriou ,  Robert Galbraith ,  Adrian C. Gerhard ,  Robert Haas ,  Xiao-Yu Hu ,  Murali N. Iyer ,  Ioannis Koltsidas ,  Timothy J. Larson ,  Steven P. Norgaard ,  Roman Pletka

IPC分类号： G06F12/00

CPC分类号： G06F11/1076 ,  G06F3/061 ,  G06F3/0662 ,  G06F3/0685

摘要： A method for optimizing locations of physical data accessed by one or more client applications interacting with a storage system, with the storage system comprising at least two redundancy groups having physical memory spaces and data bands. Each of the data bands corresponds to physical data stored on several of the physical memory spaces. A virtualized logical address space includes client data addresses utilizable by the one or more client applications. A storage controller is configured to map the client data addresses onto the data bands, such that a mapping is obtained, wherein the one or more client applications can access physical data corresponding to the data bands.

公开(公告)号：US20130046931A1

公开(公告)日：2013-02-21

申请号：US13209514

申请日：2011-08-15

申请人： Evangelos S. Eleftheriou ,  Robert Galbraith ,  Adrian C. Gerhard ,  Robert Haas ,  Xiao-Yu Hu ,  Murali N. Iyer ,  Ioannis Koltsidas ,  Timothy J. Larson ,  Steven P. Norgaard ,  Roman Pletka

发明人： Evangelos S. Eleftheriou ,  Robert Galbraith ,  Adrian C. Gerhard ,  Robert Haas ,  Xiao-Yu Hu ,  Murali N. Iyer ,  Ioannis Koltsidas ,  Timothy J. Larson ,  Steven P. Norgaard ,  Roman Pletka

IPC分类号： G06F12/08

CPC分类号： G06F11/1076 ,  G06F3/061 ,  G06F3/0662 ,  G06F3/0685

摘要： A method for optimizing locations of physical data accessed by one or more client applications interacting with a storage system, with the storage system comprising at least two redundancy groups having physical memory spaces and data bands. Each of the data bands corresponds to physical data stored on several of the physical memory spaces. A virtualized logical address space includes client data addresses utilizable by the one or more client applications. A storage controller is configured to map the client data addresses onto the data bands, such that a mapping is obtained, wherein the one or more client applications can access physical data corresponding to the data bands.

公开(公告)号：US08661196B2

公开(公告)日：2014-02-25

申请号：US13209514

申请日：2011-08-15

申请人： Evangelos S. Eleftheriou ,  Robert Galbraith ,  Adrian C. Gerhard ,  Robert Haas ,  Xiao-Yu Hu ,  Murali N. Iyer ,  Ioannis Koltsidas ,  Timothy J. Larson ,  Steven P. Norgaard ,  Roman Pletka

发明人： Evangelos S. Eleftheriou ,  Robert Galbraith ,  Adrian C. Gerhard ,  Robert Haas ,  Xiao-Yu Hu ,  Murali N. Iyer ,  Ioannis Koltsidas ,  Timothy J. Larson ,  Steven P. Norgaard ,  Roman Pletka

IPC分类号： G06F12/00

CPC分类号： G06F11/1076 ,  G06F3/061 ,  G06F3/0662 ,  G06F3/0685

摘要： A method for optimizing locations of physical data accessed by one or more client applications interacting with a storage system, with the storage system comprising at least two redundancy groups having physical memory spaces and data bands. Each of the data bands corresponds to physical data stored on several of the physical memory spaces. A virtualized logical address space includes client data addresses utilizable by the one or more client applications. A storage controller is configured to map the client data addresses onto the data bands, such that a mapping is obtained, wherein the one or more client applications can access physical data corresponding to the data bands.

摘要翻译： 一种用于优化由与存储系统交互的一个或多个客户端应用访问的物理数据的位置的方法，其中所述存储系统包括具有物理存储器空间和数据带的至少两个冗余组。 每个数据带对应于存储在几个物理存储器空间上的物理数据。 虚拟化逻辑地址空间包括由一个或多个客户端应用程序可使用的客户机数据地址。 存储控制器被配置为将客户端数据地址映射到数据带上，使得获得映射，其中一个或多个客户端应用可以访问对应于数据带的物理数据。

公开(公告)号：US08495258B2

公开(公告)日：2013-07-23

申请号：US13114124

申请日：2011-05-24

申请人： Brian E. Bakke ,  Brian L. Bowles ,  Michael J. Carnevale ,  Robert E. Galbraith, II ,  Adrian C. Gerhard ,  Murali N. Iyer ,  Daniel F. Moertl ,  Mark J. Moran ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth ,  Donald J. Ziebarth

发明人： Brian E. Bakke ,  Brian L. Bowles ,  Michael J. Carnevale ,  Robert E. Galbraith, II ,  Adrian C. Gerhard ,  Murali N. Iyer ,  Daniel F. Moertl ,  Mark J. Moran ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth ,  Donald J. Ziebarth

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A method and controller for implementing storage adapter performance optimization with automatic chained hardware operations eliminating firmware operations, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines and a control store configured to store a plurality of control blocks. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A plurality of the control blocks is selectively arranged in a respective predefined chain to define sequences of hardware operations. An automatic hardware structure is configured to build the respective predefined chain controlling the hardware operations for a predefined hardware function. The predefined hardware function includes buffer allocation and automatic DMA data from a host system to the controller for write operations, eliminating firmware operations.

摘要翻译： 一种用于实现存储适配器性能优化的方法和控制器，其具有消除固件操作的自动链接硬件操作以及提供主题控制器电路所在的设计结构。 控制器包括多个硬件引擎和被配置为存储多个控制块的控制存储器。 每个控制块被设计成控制多个硬件引擎之一的硬件操作。 多个控制块被选择性地布置在相应的预定链中以定义硬件操作的顺序。 自动硬件结构被配置为构建控制用于预定义硬件功能的硬件操作的相应预定义链。 预定义的硬件功能包括从主机系统到控制器的写入操作的缓冲区分配和自动DMA数据，从而消除了固件操作。

公开(公告)号：US20120303883A1

公开(公告)日：2012-11-29

申请号：US13114185

申请日：2011-05-24

申请人： Brian E. Bakke ,  Brian L. Bowles ,  Michael J. Carnevale ,  Robert E. Galbraith, II ,  Adrian C. Gerhard ,  Murali N. Iyer ,  Daniel F. Moertl ,  Mark J. Moran ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth ,  Donald J. Ziebarth

发明人： Brian E. Bakke ,  Brian L. Bowles ,  Michael J. Carnevale ,  Robert E. Galbraith, II ,  Adrian C. Gerhard ,  Murali N. Iyer ,  Daniel F. Moertl ,  Mark J. Moran ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth ,  Donald J. Ziebarth

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/00 ,  G06F11/108 ,  G06F11/2071 ,  G06F12/08 ,  G06F12/0868 ,  G06F2211/1009 ,  G06F2211/1059 ,  G06F2212/1016 ,  G06F2212/225 ,  G06F2212/286

摘要： A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.

摘要翻译： 一种用于实现存储适配器性能优化的方法和控制器，其中缓存数据和双重适配器之间的缓存目录镜像最小化固件操作，以及提供主题控制器电路所在的设计结构。 第一控制器或第二控制器中的一个以第一启动器模式操作，包括固件，用于建立向每个页索引建立数据帧的启动器写入操作和用于每个页索引的相应高速缓存行（CL）到另一控制器 第二目标模式。 各发起者硬件引擎传送数据，从启动器控制存储器读取CL，并将更新后的CL写入发起者数据存储器，同时向其他控制器发送数据和更新的CL。 各个目标硬件引擎将数据和更新的CL写入目标数据存储，消除了在第二目标模式下操作的控制器的固件操作。

公开(公告)号：US08868828B2

公开(公告)日：2014-10-21

申请号：US13114185

申请日：2011-05-24

申请人： Brian E. Bakke ,  Brian L. Bowles ,  Michael J. Carnevale ,  Robert E. Galbraith, II ,  Adrian C. Gerhard ,  Murali N. Iyer ,  Daniel F. Moertl ,  Mark J. Moran ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth ,  Donald J. Ziebarth

发明人： Brian E. Bakke ,  Brian L. Bowles ,  Michael J. Carnevale ,  Robert E. Galbraith, II ,  Adrian C. Gerhard ,  Murali N. Iyer ,  Daniel F. Moertl ,  Mark J. Moran ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth ,  Donald J. Ziebarth

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/00 ,  G06F11/108 ,  G06F11/2071 ,  G06F12/08 ,  G06F12/0868 ,  G06F2211/1009 ,  G06F2211/1059 ,  G06F2212/1016 ,  G06F2212/225 ,  G06F2212/286

摘要： A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.

摘要翻译： 一种用于实现存储适配器性能优化的方法和控制器，其中缓存数据和双重适配器之间的缓存目录镜像最小化固件操作，以及提供主题控制器电路所在的设计结构。 第一控制器或第二控制器中的一个以第一启动器模式操作，包括固件，用于建立向每个页索引建立数据帧的启动器写入操作和用于每个页索引的相应高速缓存行（CL）到另一控制器 第二目标模式。 各发起者硬件引擎传送数据，从启动器控制存储器读取CL，并将更新后的CL写入发起者数据存储器，同时向其他控制器发送数据和更新的CL。 各个目标硬件引擎将数据和更新的CL写入目标数据存储，消除了在第二目标模式下操作的控制器的固件操作。

公开(公告)号：US20120303909A1

公开(公告)日：2012-11-29

申请号：US13114390

申请日：2011-05-24

申请人： Brian E. Bakke ,  Brian L. Bowles ,  Michael J. Carnevale ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Murali N. Iyer ,  Daniel F. Moertl ,  Mark J. Moran ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth ,  Donald J. Ziebarth

发明人： Brian E. Bakke ,  Brian L. Bowles ,  Michael J. Carnevale ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Murali N. Iyer ,  Daniel F. Moertl ,  Mark J. Moran ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth ,  Donald J. Ziebarth

IPC分类号： G06F12/00

CPC分类号： G06F3/0689 ,  G06F3/0611 ,  G06F3/0658 ,  G06F3/0659 ,  G06F11/108 ,  G06F2211/1009

摘要： A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor.

摘要翻译： 一种用于实现具有链接硬件操作的存储适配器性能优化的方法和控制器以及最小化硬件和固件交互的增强的硬件（HW）和固件（FW）接口，以及提供主题控制器电路所在的设计结构。 控制器包括多个硬件引擎; 和处理器。 数据存储器被配置为存储多个控制块。 全局工作队列包括选择性地布置在预定义链中以定义硬件操作序列的多个控制块。 全局工作队列包括耦合到处理器和硬件引擎的队列输入以及耦合到硬件引擎的输出。 控制块被布置在各自的引擎工作队列中，其被设计成控制各个硬件引擎的硬件操作，并且各个控制块被布置在事件队列中以向处理器提供完成结果。

公开(公告)号：US20120303886A1

公开(公告)日：2012-11-29

申请号：US13114291

申请日：2011-05-24

申请人： Brian E. Bakke ,  Brian L. Bowles ,  Michael J. Carnevale ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Murali N. Iyer ,  Daniel F. Moertl ,  Mark J. Moran ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth ,  Donald J. Ziebarth

发明人： Brian E. Bakke ,  Brian L. Bowles ,  Michael J. Carnevale ,  Robert E. Galbraith ,  Adrian C. Gerhard ,  Murali N. Iyer ,  Daniel F. Moertl ,  Mark J. Moran ,  Gowrisankar Radhakrishnan ,  Rick A. Weckwerth ,  Donald J. Ziebarth

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F3/061 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0689 ,  G06F12/0866

摘要： A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance.

摘要翻译： 一种用于通过配置成实现最小化硬件和固件交互的特定性能路径的预定义的硬件操作链来实现存储适配器性能优化的方法和控制器以及提供所述对象控制器电路所在的设计结构。 控制器包括多个硬件引擎; 以及数据存储器，被配置为存储选择性地布置在多个预定义链中的一个中的多个控制块。 每个预定义链定义一系列操作。 每个控制块被设计成控制多个硬件引擎之一的硬件操作。 资源句柄结构被配置为基于系统的特定特征来选择预定义的链。 每个预定义链被配置为实现特定的性能路径以最大化性能。