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1.发明申请Automated Method for Validating Manufacturing Test Rules Pertaining to an Electronic Component 有权用于验证与电子部件有关的制造测试规则的自动化方法公开(公告)号：US20100042396A1
公开(公告)日：2010-02-18
申请号：US12191538
申请日：2008-08-14
IPC分类号： G06G7/62
CPC分类号： G06F11/263 , G06F11/261
摘要： The invention is generally directed to a method and apparatus for validating a specified manufacturing test rule, which pertains to an electronic component. One embodiment comprising a method includes the step of generating a file of test data sets, wherein each test data set in the file is valid for the rule. Each test data set includes a stimulus comprising one or more single input vectors, and further includes a set of results that are expected, when the stimulus is applied to the electronic component. The method further comprises constructing a testbench to prepare each of a plurality of testcases for simulation, wherein each testcase corresponds to the stimulus and the expected output results of one of the test data sets, and each testcase is disposed to be simulated separately, or independently, from every other testcase. The method further comprises selectively preparing each of the testcases for simulation, in order to provide simulated results for the stimulus corresponding to each testcase. The expected results and the simulated results are compared for each testcase, in order to determine whether there are any differences therebetween. Each of the above steps can be carried out using means that are completely automated. Thus, the entire method for validating manufacturing test rules can likewise be completely automated. Also, the processing applied to different test cases can occur simultaneously or in parallel, to substantially reduce the processing burden.
摘要翻译： 本发明一般涉及用于验证与电子部件有关的特定制造测试规则的方法和装置。 包括方法的一个实施例包括生成测试数据集的文件的步骤，其中文件中设置的每个测试数据对于该规则是有效的。 每个测试数据集包括包括一个或多个单个输入向量的刺激，并且还包括当将刺激应用于电子部件时预期的一组结果。 该方法还包括构建测试台以准备用于模拟的多个测试箱中的每一个，其中每个测试用例对应于一个测试数据组的刺激和预期输出结果，并且每个测试用例被设置为单独模拟或独立地模拟 ，从每个其他测试用例。 该方法还包括选择性地准备每个用于模拟的测试箱，以便提供对应于每个测试箱的刺激的模拟结果。 对每个测试用例比较预期结果和模拟结果，以确定它们之间是否存在差异。 可以使用完全自动化的装置来执行上述步骤中的每一个。 因此，用于验证制造测试规则的整个方法同样可以完全自动化。 此外，应用于不同测试用例的处理可以同时或并行地发生，从而大大减少处理负担。
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公开(公告)号：US08136059B2
公开(公告)日：2012-03-13
申请号：US12257610
申请日：2008-10-24
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Illustrative embodiments provide a computer-implemented method for resolving indeterminate states by inserting logic into a design. The computer-implemented method receives an original design input from a requester to form a received input and determines whether the received input contains an indeterminate output. Responsive to a determination that the received input contains an indeterminate output, the computer-implemented method generates a temporary design from the received input, wherein the temporary design contains “unique” output and all inputs, updates the temporary design, and synthesizes the original design and each temporary design individually to form a synthesized original design and a set of synthesized temporary designs. The computer-implemented method merges the synthesized original design with the set of synthesized temporary design to form a final design; and returns the final design to the requester.
摘要翻译： 说明性实施例提供了一种用于通过将逻辑插入到设计中来解决不确定状态的计算机实现的方法。 计算机实现的方法从请求者接收原始设计输入以形成接收到的输入，并确定接收的输入是否包含不确定的输出。 响应于确定接收到的输入包含不确定的输出，计算机实现的方法从接收到的输入生成临时设计，其中临时设计包含“唯一”输出和所有输入，更新临时设计，并且合成原始设计 和每个临时设计单独形成合成的原始设计和一组合成的临时设计。 计算机实现的方法将合成原始设计与合成临时设计集合合并形成最终设计; 并将最终设计返回给请求者。
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3.发明授权公开(公告)号：US08135571B2
公开(公告)日：2012-03-13
申请号：US12191538
申请日：2008-08-14
CPC分类号： G06F11/263 , G06F11/261
摘要： The invention is directed to validating a specified manufacturing test rule, which pertains to an electronic component. The method includes generating a file of test data sets, wherein each test data set in the file is valid for the rule. Each test data set includes a stimulus comprising one or more single input vectors, and further includes a set of results that are expected. The method further comprises constructing a testbench to prepare testcases for simulation, wherein each testcase corresponds to the stimulus and the expected output results of one of the test data sets, and each testcase is disposed to be simulated separately, or independently, from every other testcase. The method further comprises selectively preparing each of the testcases for simulation, in order to provide simulated results for the stimulus corresponding to each testcase. The expected results and the simulated results are compared for each testcase.
摘要翻译： 本发明旨在验证涉及电子部件的指定制造测试规则。 该方法包括生成测试数据集的文件，其中文件中设置的每个测试数据对于该规则是有效的。 每个测试数据集包括包括一个或多个单个输入向量的刺激，并且还包括预期的一组结果。 该方法还包括构建测试台以准备用于模拟的测试用例，其中每个测试用例对应于一个测试数据组的激励和预期输出结果，并且每个测试用例被设置为单独地或独立地从每个其他测试用例模拟 。 该方法还包括选择性地准备每个用于模拟的测试箱，以便提供对应于每个测试箱的刺激的模拟结果。 对每个测试用例比较预期结果和模拟结果。
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4.发明授权Automatically creating manufacturing test rules pertaining to an electronic component 有权自动创建与电子元件相关的制造测试规则公开(公告)号：US08065641B2
公开(公告)日：2011-11-22
申请号：US12203038
申请日：2008-09-02
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A system for creating manufacturing test rules. Stimuli for an electronic design are generated automatically by a stimuli generator. The stimuli generator takes into account certain limitations of the design when automatically generating the manufacturing test rules. The design is tested by a testbench using the stimuli. A simulation log for the design is generated by the testbench. The simulation log is then processed by a simulation log processor. An HDL representation of the design is generated by the simulation log processor using the processed simulation log. A gate-level version of the design is generated by a synthesis tool using the HDL representation of the design. The gate-level version of the design is further processed by the synthesis tool to make any necessary modifications. Then, the gate-level version of the design is outputted as the final manufacturing test rule. Thus, creating manufacturing test rules can be completely automated.
摘要翻译： 用于创建制造测试规则的系统。 电子设计的刺激是由刺激发生器自动产生的。 当自动生成制造测试规则时，刺激发生器考虑到设计的某些限制。 该设计由使用刺激的测试台进行测试。 该设计的仿真日志由测试平台生成。 仿真日志由仿真日志处理器处理。 设计的HDL表示由仿真日志处理器使用处理的仿真日志生成。 设计的门级版本由使用设计的HDL表示的综合工具生成。 设计的门级版本由综合工具进一步处理，以进行任何必要的修改。 然后，设计的门级版本作为最终制造测试规则输出。 因此，创建制造测试规则可以完全自动化。
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公开(公告)号：US20100107129A1
公开(公告)日：2010-04-29
申请号：US12257610
申请日：2008-10-24
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Illustrative embodiments provide a computer-implemented method for resolving indeterminate states by inserting logic into a design. The computer-implemented method receives an original design input from a requester to form a received input and determines whether the received input contains an indeterminate output. Responsive to a determination that the received input contains an indeterminate output, the computer-implemented method generates a temporary design from the received input, wherein the temporary design contains “unique” output and all inputs, updates the temporary design, and synthesizes the original design and each temporary design individually to form a synthesized original design and a set of synthesized temporary designs. The computer-implemented method merges the synthesized original design with the set of synthesized temporary design to form a final design; and returns the final design to the requester.
摘要翻译： 说明性实施例提供了一种用于通过将逻辑插入到设计中来解决不确定状态的计算机实现的方法。 计算机实现的方法从请求者接收原始设计输入以形成接收到的输入，并确定接收的输入是否包含不确定的输出。 响应于确定接收到的输入包含不确定的输出，计算机实现的方法从接收到的输入生成临时设计，其中临时设计包含“唯一”输出和所有输入，更新临时设计，并且合成原始设计 和每个临时设计单独形成合成的原始设计和一组合成的临时设计。 计算机实现的方法将合成原始设计与合成临时设计集合合并形成最终设计; 并将最终设计返回给请求者。
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6.发明申请公开(公告)号：US20100057425A1
公开(公告)日：2010-03-04
申请号：US12203038
申请日：2008-09-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A system for creating manufacturing test rules. Stimuli for an electronic design are generated automatically by a stimuli generator. The stimuli generator takes into account certain limitations of the design when automatically generating the manufacturing test rules. The design is tested by a testbench using the stimuli. A simulation log for the design is generated by the testbench. The simulation log is then processed by a simulation log processor. An HDL representation of the design is generated by the simulation log processor using the processed simulation log. A gate-level version of the design is generated by a synthesis tool using the HDL representation of the design. The gate-level version of the design is further processed by the synthesis tool to make any necessary modifications. Then, the gate-level version of the design is outputted as the final manufacturing test rule. Thus, creating manufacturing test rules can be completely automated.
摘要翻译： 用于创建制造测试规则的系统。 电子设计的刺激是由刺激发生器自动产生的。 当自动生成制造测试规则时，刺激发生器考虑到设计的某些限制。 该设计由使用刺激的测试台进行测试。 该设计的仿真日志由测试平台生成。 仿真日志由仿真日志处理器处理。 设计的HDL表示由仿真日志处理器使用处理的仿真日志生成。 设计的门级版本由使用设计的HDL表示的综合工具生成。 设计的门级版本由综合工具进一步处理，以进行任何必要的修改。 然后，设计的门级版本作为最终制造测试规则输出。 因此，创建制造测试规则可以完全自动化。
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7.发明授权System for asserting burst termination signal and burst complete signal one cycle prior to and during last cycle in fixed length burst transfers 失效用于在固定长度突发传输中在上一周期之前和之后一个周期断言突发终止信号和突发完整信号的系统
公开(公告)号：US6052745A
公开(公告)日：2000-04-18
申请号：US96943
申请日：1998-06-12
申请人： Michael Raymond Miller , John Patrick McCardle, II , Michael Patrick Muhlada , Mark Michael Schaffer , Christopher Randall Starr
发明人： Michael Raymond Miller , John Patrick McCardle, II , Michael Patrick Muhlada , Mark Michael Schaffer , Christopher Randall Starr
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention provides a method and system for fixed length bursts of data on a bus within a data processing system. The method and system in accordance with the present invention provides a burst transfer protocol which includes the providing of length information of a fixed length burst of data on a signal from at least one master device to at least one slave device when the at least one master device requests the fixed length burst of data. It also includes the asserting of a burst termination signal by the at least one slave device one cycle prior to a last cycle in the fixed length burst, and the asserting of a burst complete signal during the last cycle in the fixed length burst for a write burst, or one cycle prior to the last cycle in the fixed length burst for a read burst, based on the value of the signal. This burst transfer protocol enables burst transfers of a maximum length to be performed across a local bus between a master and a slave without dead cycle penalties after the transfer. This improves the efficiency and performance of data throughput across the local bus without the need to increase the frequency. The present invention requires no new signals and is optional so a master and slave who use the protocol of the present invention is compatible with masters and slaves who do not.
摘要翻译： 本发明提供了一种在数据处理系统内的总线上的数据的固定长度突发的方法和系统。 根据本发明的方法和系统提供突发传输协议，其包括当至少一个主设备从至少一个主设备到至少一个从设备的信号时提供固定长度的数据突发数据长度信息 设备请求固定长度的数据突发。 它还包括在固定长度脉冲串中的最后一个周期之前一个周期由至少一个从设备断言突发终止信号，以及在固定长度脉冲串中的最后一个周期期间断言突发完成信号以进行写入 基于信号的值，在针对读取脉冲串的固定长度脉冲串中的最后一个周期之前的一个周期。 该突发传输协议允许在主机和从机之间的本地总线上执行最大长度的突发传输，而在传输之后不会造成死循环损坏。 这样可以提高局部总线上数据吞吐量的效率和性能，而无需增加频率。 本发明不需要新的信号并且是可选的，所以使用本发明的协议的主设备和从设备与没有的主设备和从设备兼容。
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8.发明授权
公开(公告)号：US5760784A
公开(公告)日：1998-06-02
申请号：US589212
申请日：1996-01-22
CPC分类号： G06T9/00
摘要： Video data is decompressed in a coder/decoder (CODEC) and then scaled in a scaler device before being provided to a frame buffer within a display adapter of a data processing system. Since the scaling of the video data often results in a significant increase in the required bandwidth, a buffer implemented within the scaling device may reach a threshold level whereby it is not desired that any more scaled data be received before being transmitted to the frame buffer. When such a threshold level is reached, a stall signal is sent to the interface between the scaler device and the CODEC device providing the pixel data, which results in the stopping of the transmission of pixel data from the CODEC to the scaler device. Assertion of the stall signal results in the suspension of the transmission of the horizontal and vertical synchronization signals and the pixel clock signal from the scaler device to the CODEC device.
摘要翻译： 视频数据在编码器/解码器（CODEC）中解压缩，然后在缩放器装置中被缩放，然后提供给数据处理系统的显示适配器内的帧缓冲器。 由于视频数据的缩放通常导致所需带宽的显着增加，所以在缩放设备内实现的缓冲器可能达到阈值水平，因此不希望在发送到帧缓冲器之前接收任何更多的缩放数据。 当达到这样的阈值电平时，向缩放器装置和提供像素数据的CODEC装置之间的接口发送失速信号，这导致停止从CODEC到缩放装置的像素数据传输。 失速信号的断言导致水平和垂直同步信号和像素时钟信号从缩放器装置传输到CODEC装置的暂停。
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