公开(公告)号：US6052745A

公开(公告)日：2000-04-18

申请号：US96943

申请日：1998-06-12

申请人： Michael Raymond Miller ,  John Patrick McCardle, II ,  Michael Patrick Muhlada ,  Mark Michael Schaffer ,  Christopher Randall Starr

发明人： Michael Raymond Miller ,  John Patrick McCardle, II ,  Michael Patrick Muhlada ,  Mark Michael Schaffer ,  Christopher Randall Starr

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： The present invention provides a method and system for fixed length bursts of data on a bus within a data processing system. The method and system in accordance with the present invention provides a burst transfer protocol which includes the providing of length information of a fixed length burst of data on a signal from at least one master device to at least one slave device when the at least one master device requests the fixed length burst of data. It also includes the asserting of a burst termination signal by the at least one slave device one cycle prior to a last cycle in the fixed length burst, and the asserting of a burst complete signal during the last cycle in the fixed length burst for a write burst, or one cycle prior to the last cycle in the fixed length burst for a read burst, based on the value of the signal. This burst transfer protocol enables burst transfers of a maximum length to be performed across a local bus between a master and a slave without dead cycle penalties after the transfer. This improves the efficiency and performance of data throughput across the local bus without the need to increase the frequency. The present invention requires no new signals and is optional so a master and slave who use the protocol of the present invention is compatible with masters and slaves who do not.

摘要翻译： 本发明提供了一种在数据处理系统内的总线上的数据的固定长度突发的方法和系统。 根据本发明的方法和系统提供突发传输协议，其包括当至少一个主设备从至少一个主设备到至少一个从设备的信号时提供固定长度的数据突发数据长度信息 设备请求固定长度的数据突发。 它还包括在固定长度脉冲串中的最后一个周期之前一个周期由至少一个从设备断言突发终止信号，以及在固定长度脉冲串中的最后一个周期期间断言突发完成信号以进行写入 基于信号的值，在针对读取脉冲串的固定长度脉冲串中的最后一个周期之前的一个周期。 该突发传输协议允许在主机和从机之间的本地总线上执行最大长度的突发传输，而在传输之后不会造成死循环损坏。 这样可以提高局部总线上数据吞吐量的效率和性能，而无需增加频率。 本发明不需要新的信号并且是可选的，所以使用本发明的协议的主设备和从设备与没有的主设备和从设备兼容。

公开(公告)号：US07913021B2

公开(公告)日：2011-03-22

申请号：US11565041

申请日：2006-11-30

申请人： Richard Gerard Hofmann ,  Mark Michael Schaffer

发明人： Richard Gerard Hofmann ,  Mark Michael Schaffer

IPC分类号： G06F13/14 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/4265

摘要： A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.

摘要翻译： 公开了一种具有通过总线连接的发送部件和接收部件的处理系统。 总线可以配置有第一和第二通道。 发送组件可以被配置为在第一通道上广播读取和写入地址信息，读取和写入控制信号以及写入数据。 发送组件还可以被配置为向接收组件发信号，使得接收组件可以区分读取和写入地址信息，读取和写入控制信号以及在第一通道上广播的写入数据。 接收部件可以被配置为基于写入地址信息和写入控制信号在第一信道上存储写入数据，基于读取的地址信息和读取的控制信号来检索读取的数据，并将检索到的读取数据广播到 第二个渠道。

公开(公告)号：US5926831A

公开(公告)日：1999-07-20

申请号：US731350

申请日：1996-10-11

申请人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer ,  James N. Dieffenderfer

发明人： Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer ,  James N. Dieffenderfer

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0215

摘要： A dynamically configured memory controller to prevent speculative memory accesses of non-well behaved memory. Such dynamic configuration of a memory controller may be accomplished by providing to the memory controller guard information associated with memory requests. The memory controller may then prevent speculative memory accesses when the guard information indicates that the memory requests are of non-well behaved memory. The guard information provided to the memory controller may include guard information associated with each memory request provided to the memory controller.

摘要翻译： 一种动态配置的存储器控​​制器，用于防止对非良好行为内存的推测性内存访问。 可以通过向存储器控制器提供与存储器请求相关联的保护信息来实现存储器控制器的这种动态配置。 当保护信息指示存储器请求是非良好的存储器时，存储器控制器可以防止推测存储器访问。 提供给存储器控制器的保护信息可以包括与提供给存储器控制器的每个存储器请求相关联的保护信息。

公开(公告)号：US08615638B2

公开(公告)日：2013-12-24

申请号：US12900857

申请日：2010-10-08

申请人： Martyn Ryan Shirlen ,  Richard Gerard Hofmann ,  Mark Michael Schaffer

发明人： Martyn Ryan Shirlen ,  Richard Gerard Hofmann ,  Mark Michael Schaffer

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F13/1689 ,  G06F12/0215

摘要： Memory controllers, systems, methods, and computer-readable mediums for applying a page management policy(ies) based on stream transaction information are disclosed. In one embodiment, a memory controller is provided and configured to receive memory access requests for stream transactions. The memory controller is configured to perform a memory access to a memory page(s) in memory included in the stream transaction. The controller is further configured to apply a page management policy(ies) to the memory page(s) in memory based on information related to the stream transactions. In this manner, the page management policy(ies) can be configured to utilize page open policies for efficiency that stream transactions may facilitate, but while also recognizing and taking into consideration in the page management policy latency issues that can arise when the memory controller is handling memory access requests from different devices.

摘要翻译： 公开了用于基于流交易信息应用页面管理策略的内存控制器，系统，方法和计算机可读介质。 在一个实施例中，存储器控制器被提供并被配置为接收流事务的存储器访问请求。 存储器控制器被配置为对包含在流事务中的存储器中的存储器页执行存储器访问。 控制器还被配置为基于与流事务相关的信息将页面管理策略应用于存储器中的存储器页面。 以这种方式，页面管理策略可以被配置为利用页面打开的策略来实现流交易可以促进的效率，但是在存储器控制器是可能出现的页面管理策略延迟问题的同时还识别和考虑 处理来自不同设备的存储器访问请求。

公开(公告)号：US07209998B2

公开(公告)日：2007-04-24

申请号：US10921053

申请日：2004-08-17

申请人： Richard Gerard Hofmann ,  Mark Michael Schaffer

发明人： Richard Gerard Hofmann ,  Mark Michael Schaffer

IPC分类号： G06F13/14 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/4265

摘要： A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.

摘要翻译： 公开了一种具有通过总线连接的发送部件和接收部件的处理系统。 总线可以配置有第一和第二通道。 发送组件可以被配置为在第一通道上广播读取和写入地址信息，读取和写入控制信号以及写入数据。 发送组件还可以被配置为向接收组件发信号，使得接收组件可以区分读取和写入地址信息，读取和写入控制信号以及在第一通道上广播的写入数据。 接收部件可以被配置为基于写入地址信息和写入控制信号在第一信道上存储写入数据，基于读取的地址信息和读取的控制信号来检索读取的数据，并将检索到的读取数据广播到 第二个渠道。

公开(公告)号：US6047336A

公开(公告)日：2000-04-04

申请号：US39645

申请日：1998-03-16

申请人： Edward Hammond Green, III ,  Richard Gerard Hofmann ,  Mark Michael Schaffer ,  Dennis Charles Wilkerson

发明人： Edward Hammond Green, III ,  Richard Gerard Hofmann ,  Mark Michael Schaffer ,  Dennis Charles Wilkerson

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A DMA Controller, in response to a data transfer request from a slave device, initiates a memory transfer cycle and informs the slave device when the data transfer has completed. In order to avoid dead clock cycles on internal bus(es), the DMA Controller initiates a speculative data transfer cycle after the notification. The DMA Controller aborts the speculative data transfer cycle if the slave device does not request another data transfer within a predetermined time.

摘要翻译： DMA控制器响应来自从设备的数据传输请求，启动存储器传送周期并在数据传输完成时通知从设备。 为了避免内部总线上的死时钟周期，DMA控制器在通知后启动推测数据传输周期。 如果从设备在预定时间内没有请求另一个数据传输，则DMA控制器中止推测数据传输周期。

公开(公告)号：US08861410B2

公开(公告)日：2014-10-14

申请号：US13285215

申请日：2011-10-31

申请人： Jaya Prakash Subramaniam Ganasan ,  Prudhvi N. Nooney ,  Darren P. Umstead ,  Joseph L. Van Swearingen ,  Barry Joe Wolford ,  Mark Michael Schaffer

发明人： Jaya Prakash Subramaniam Ganasan ,  Prudhvi N. Nooney ,  Darren P. Umstead ,  Joseph L. Van Swearingen ,  Barry Joe Wolford ,  Mark Michael Schaffer

IPC分类号： H04B7/00

CPC分类号： H04L45/74

摘要： A transaction request passes from an initiator through interconnect paths and a routing ID indicating the interconnect paths is prepended. A temporary ID is assigned to the routing ID, the transaction request with the temporary ID is sent to a target device, and a response having the temporary ID is received. The routing ID is retrieved using the target ID, and the response with the retrieved routing ID is sent to the initiator.

摘要翻译： 交易请求从发起者通过互连路径传递，并且指示互连路径的路由ID被添加。 临时ID被分配给路由ID，具有临时ID的事务请求被发送到目标设备，并且接收到具有临时ID的响应。 使用目标ID检索路由ID，并将具有检索到的路由ID的响应发送到启动器。

公开(公告)号：US08838861B2

公开(公告)日：2014-09-16

申请号：US13531863

申请日：2012-06-25

申请人： Martyn Ryan Shirlen ,  Mark Michael Schaffer

发明人： Martyn Ryan Shirlen ,  Mark Michael Schaffer

IPC分类号： G06F11/36

CPC分类号： G06F11/3656 ,  G06F11/364 ,  G06F13/4022

摘要： Systems and methods for trace multicast across a bus structure are provided. Preferably, the bus structure is that of a System-on-a-Chip (SoC), where the SoC includes a number of master components and a number of slave components connected via the bus structure. The bus structure supports a trace multicast feature. In one embodiment, the bus structure receives a bus transaction from a master component and, in response, outputs the bus transaction to a corresponding slave port. In addition, the bus structure determines whether a trace multicast is desired for the bus transaction. If a trace multicast is desired, the bus structure generates an additional bus transaction having one or more transaction attributes that include a translated version of the bus transaction and outputs the additional bus transaction to a trace slave port of the bus structure. The trace multicast feature provides a non-invasive mechanism for driver-level trace.

摘要翻译： 提供了通过总线结构跟踪组播的系统和方法。 优选地，总线结构是片上系统（SoC）的结构，其中SoC包括多个主组件和通过总线结构连接的多个从组件。 总线结构支持跟踪组播功能。 在一个实施例中，总线结构从主组件接收总线事务，并且作为响应，将总线事务输出到对应的从端口。 此外，总线结构确定对于总线事务是否需要跟踪多播。 如果需要跟踪多播，则总线结构生成具有一个或多个事务属性的附加总线事务，该事务属性包括总线事务的转换版本，并将附加总线事务输出到总线结构的跟踪从站端口。 跟踪多播功能为驱动程序级跟踪提供了非侵入性机制。

公开(公告)号：US20120089789A1

公开(公告)日：2012-04-12

申请号：US12900857

申请日：2010-10-08

申请人： Martyn Ryan Shirlen ,  Richard Gerard Hofmann ,  Mark Michael Schaffer

发明人： Martyn Ryan Shirlen ,  Richard Gerard Hofmann ,  Mark Michael Schaffer

IPC分类号： G06F12/00

CPC分类号： G06F13/1689 ,  G06F12/0215

摘要： Memory controllers, systems, methods, and computer-readable mediums for applying a page management policy(ies) based on stream transaction information are disclosed. In one embodiment, a memory controller is provided and configured to receive memory access requests for stream transactions. The memory controller is configured to perform a memory access to a memory page(s) in memory included in the stream transaction. The controller is further configured to apply a page management policy(ies) to the memory page(s) in memory based on information related to the stream transactions. In this manner, the page management policy(ies) can be configured to utilize page open policies for efficiency that stream transactions may facilitate, but while also recognizing and taking into consideration in the page management policy latency issues that can arise when the memory controller is handling memory access requests from different devices.

摘要翻译： 公开了用于基于流交易信息应用页面管理策略的内存控制器，系统，方法和计算机可读介质。 在一个实施例中，存储器控制器被提供并被配置为接收流事务的存储器访问请求。 存储器控制器被配置为对包含在流事务中的存储器中的存储器页执行存储器访问。 控制器还被配置为基于与流事务相关的信息将页面管理策略应用于存储器中的存储器页面。 以这种方式，页面管理策略可以被配置为利用页面打开的策略来实现流交易可以促进的效率，但是在存储器控制器是可能出现的页面管理策略延迟问题的同时还识别和考虑 处理来自不同设备的存储器访问请求。

公开(公告)号：US20120089759A1

公开(公告)日：2012-04-12

申请号：US12900800

申请日：2010-10-08

申请人： Martyn Ryan Shirlen ,  Richard Gerard Hofmann ,  Mark Michael Schaffer

发明人： Martyn Ryan Shirlen ,  Richard Gerard Hofmann ,  Mark Michael Schaffer

IPC分类号： G06F13/362

CPC分类号： G06F13/362

摘要： Devices, systems, methods, and computer-readable mediums for arbitrating stream transactions based on information related to the stream transactions are disclosed. A stream transaction is a superset of burst access types to facilitate efficient bulk transfers of data. In one embodiment, an arbiter is provided that arbitrates bus transactions between a plurality of devices coupled to a bus competing for resources accessible through the bus. To efficiently arbitrate stream transactions requested on the bus, the arbiter is configured to use information related to the stream transactions to provide a view of future bus traffic on the bus. The arbiter is configured to use this stream transaction information to apply bus arbitration policies for arbitrating stream transactions. In this example, the bus arbitration policy can be adjusted for stream transactions based on the stream transaction information, if necessary, for the arbiter to attempt to meet a parameter(s) for completing the stream transactions.

摘要翻译： 公开了用于基于与流事务相关的信息来仲裁流事务的设备，系统，方法和计算机可读介质。 流事务是突发访问类型的超集，以便于数据的高效批量传输。 在一个实施例中，提供仲裁器，其仲裁耦合到总线的多个设备之间的总线事务，该总线竞争通过总线可访问的资源。 为了有效地仲裁在总线上请求的流事务，仲裁器被配置为使用与流事务相关的信息来提供总线上未来总线流量的视图。 仲裁器被配置为使用该流事务信息来应用用于仲裁流事务的总线仲裁策略。 在该示例中，如果需要，可以基于流交易信息来调整总线仲裁策略，以便仲裁者尝试满足用于完成流事务的参数。