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    Augmenting of automated clustering-based trace sampling methods by user-directed phase detection
    1.
    发明授权
    Augmenting of automated clustering-based trace sampling methods by user-directed phase detection 有权
    通过用户导向的相位检测来增强基于自动聚类的跟踪采样方法

    公开(公告)号：US08000953B2

    公开(公告)日：2011-08-16

    申请号：US11842337

    申请日：2007-08-21

    申请人： Robert H. Bell, Jr. ,  Wen-Tzer Thomas Chen ,  Pattabi R. Seshadri ,  John-David Wellman

    发明人： Robert H. Bell, Jr. ,  Wen-Tzer Thomas Chen ,  Pattabi R. Seshadri ,  John-David Wellman

    IPC分类号： G06F9/45

    CPC分类号： G06F9/455 ,  G06F11/3636 ,  G06F11/3664

    摘要： Computer implemented method, system, and computer usable program code for simulating processor operation in a data processing system. An instruction trace is generated, wherein the instruction trace includes markers specified by a user for identifying interval boundaries for at least one interval of the instruction trace. The instruction trace is divided into a plurality of intervals in consideration of the markers, and the plurality of intervals are formed into a plurality of interval clusters, wherein each interval cluster represents one phase of execution of the instruction trace. At least one interval from each of the plurality of interval clusters is selected as a trace sample to provide a plurality of trace samples, wherein each selected interval is of at least a minimum size, a simulation is performed using the plurality of trace samples, and a result of the simulation is provided to the user.

    摘要翻译： 用于在数据处理系统中模拟处理器操作的计算机实现的方法，系统和计算机可用程序代码。 生成指令轨迹，其中指令轨迹包括由用户指定的用于识别指令轨迹的至少一个间隔的间隔边界的标记。 考虑到标记，指令轨迹被分成多个间隔，并且多个间隔被形成为多个间隔簇，其中每个间隔簇表示指令轨迹的执行的一个阶段。 选择来自多个间隔群集中的每一个的至少一个间隔作为跟踪样本以提供多个跟踪样本，其中每个选择的间隔至少为最小尺寸，使用多个迹线样本进行模拟，以及 向用户提供模拟的结果。

    Augmenting of Automated Clustering-Based Trace Sampling Methods by User-Directed Phase Detection
    2.
    发明申请
    Augmenting of Automated Clustering-Based Trace Sampling Methods by User-Directed Phase Detection 有权
    通过用户定向相位检测来增强基于自动聚类的跟踪采样方法

    公开(公告)号：US20090055153A1

    公开(公告)日：2009-02-26

    申请号：US11842337

    申请日：2007-08-21

    申请人： Robert H. Bell, JR. ,  Wen-Tzer Thomas Chen ,  Pattabi R. Seshadri ,  John-David Wellman

    发明人： Robert H. Bell, JR. ,  Wen-Tzer Thomas Chen ,  Pattabi R. Seshadri ,  John-David Wellman

    IPC分类号： G06F9/455

    CPC分类号： G06F9/455 ,  G06F11/3636 ,  G06F11/3664

    摘要： Computer implemented method, system, and computer usable program code for simulating processor operation in a data processing system. An instruction trace is generated, wherein the instruction trace includes markers specified by a user for identifying interval boundaries for at least one interval of the instruction trace. The instruction trace is divided into a plurality of intervals in consideration of the markers, and the plurality of intervals are formed into a plurality of interval clusters, wherein each interval cluster represents one phase of execution of the instruction trace. At least one interval from each of the plurality of interval clusters is selected as a trace sample to provide a plurality of trace samples, wherein each selected interval is of at least a minimum size, a simulation is performed using the plurality of trace samples, and a result of the simulation is provided to the user.

    摘要翻译： 用于在数据处理系统中模拟处理器操作的计算机实现的方法，系统和计算机可用程序代码。 生成指令轨迹，其中指令轨迹包括由用户指定的用于识别指令轨迹的至少一个间隔的间隔边界的标记。 考虑到标记，指令轨迹被分成多个间隔，并且多个间隔被形成为多个间隔簇，其中每个间隔簇表示指令轨迹的执行的一个阶段。 选择来自多个间隔群集中的每一个的至少一个间隔作为跟踪样本以提供多个跟踪样本，其中每个选择的间隔至少为最小尺寸，使用多个迹线样本进行模拟，以及 向用户提供模拟的结果。

    Control signal memoization in a multiple instruction issue microprocessor
    6.
    发明授权
    Control signal memoization in a multiple instruction issue microprocessor 失效
    在多指令发出微处理器中控制信号记忆

    公开(公告)号：US08151092B2

    公开(公告)日：2012-04-03

    申请号：US11034284

    申请日：2005-01-12

    申请人： Erik Richter Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman ,  Victor V. Zyuban

    发明人： Erik Richter Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman ,  Victor V. Zyuban

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3808 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3873

    摘要： A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

    摘要翻译： 在微处理器管线的各个阶段提供动态预测和/或精确缓存机制，使得可以在程序执行过程中存储和存储各种控制信号。 精确的控制信号矢量缓存可以完成。 每当在指令解码，注册重命名和依赖关系检查之后形成问题组时，可以在引导指令的标签下缓存问题组信息的编码副本。 所产生的依赖性高速缓存或控制向量高速缓存可以在微处理器流水线的指令发出逻辑阶段的开始时被下一次相应的指令组出现以重新执行。 由于可以在高速缓存中的单个周期中访问编码的问题组位模式，所以具有该实施例的所得微处理器流水线可以被看作是两个并行的管道，其中如果存在依赖性高速缓存或控制向量高速缓存 击中。

    Modeling system-level effects of soft errors
    7.
    发明授权
    Modeling system-level effects of soft errors 有权
    建模软错误的系统级影响

    公开(公告)号：US08091050B2

    公开(公告)日：2012-01-03

    申请号：US12243427

    申请日：2008-10-01

    申请人： Pradip Bose ,  Prabhakar N. Kudva ,  Jude A. Rivers ,  Pia N. Sanda ,  John-David Wellman

    发明人： Pradip Bose ,  Prabhakar N. Kudva ,  Jude A. Rivers ,  Pia N. Sanda ,  John-David Wellman

    IPC分类号： G06F17/50 ,  G06F11/22

    CPC分类号： G06F17/5036 ,  G06F2217/82

    摘要： Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.

    摘要翻译： 提供了对软错误的系统级别影响进行建模的机制。 提供了在IC设计的概念阶段将器件级和组件级软错误率（SER）分析机制与微架构级性能分析工具集成的机制，从而生成SER分析工具。 通过将SER分析工具应用于IC设计，可以生成IC设计的第一个SER简档。 在IC设计的后期阶段，获得关于IC设计中逻辑和存储元件的SER漏洞的详细信息，并且基于关于SER漏洞的详细信息来改进第一SER简档，从而为IC生成第二SER简档 设计。 基于第一SER简档或第二SER简档中的一个，在IC设计的一个或多个阶段进行对IC设计的修改。

    Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
    8.
    发明授权
    Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code 有权
    以与现有代码兼容的方式扩展具有固定长度指令的处理器中指令位数目的方法和装置

    公开(公告)号：US07865699B2

    公开(公告)日：2011-01-04

    申请号：US11931815

    申请日：2007-10-31

    申请人： Erik R Altman ,  Michael Gschwind ,  David A. Luick ,  Daniel A. Prener ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman

    发明人： Erik R Altman ,  Michael Gschwind ,  David A. Luick ,  Daniel A. Prener ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3816 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/30185

    摘要： This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.

    摘要翻译： 本发明涉及存储在计算机可读介质上的装置，方法和计算机程序。 计算机程序包括与具有代码页的指令单元一起使用的指令，并且具有用于将代码页划分为至少两个部分的计算机程序代码，用于在其第一部分中存储多个指令字，并且至少与 一个指令字，用于在其第二部分中存储对第一部分中的每个指令字的扩展。 计算机程序还包括用于设置至少一个页表条目位的状态的计算机程序代码，用于通过代码页在代码页上指示代码页是否被分割成用于存储指令字的第一和第二部分，以及它们 扩展，还是包含代码页而不是仅存储指令字的单个部分。