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    CONTROL SIGNAL MEMOIZATION IN A MULTIPLE INSTRUCTION ISSUE MICROPROCESSOR
    2.
    发明申请
    CONTROL SIGNAL MEMOIZATION IN A MULTIPLE INSTRUCTION ISSUE MICROPROCESSOR 失效
    多指令问题微处理器中的控制信号记录

    公开(公告)号：US20120144166A1

    公开(公告)日：2012-06-07

    申请号：US13371181

    申请日：2012-02-10

    申请人： Erik Richter Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman ,  Victor V. Zyuban

    发明人： Erik Richter Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman ,  Victor V. Zyuban

    IPC分类号： G06F9/38 ,  G06F9/312

    CPC分类号： G06F9/3808 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3873

    摘要： A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

    摘要翻译： 在微处理器管线的各个阶段提供动态预测和/或精确缓存机制，使得可以在程序执行过程中存储和存储各种控制信号。 精确的控制信号矢量缓存可以完成。 每当在指令解码，注册重命名和依赖关系检查之后形成问题组时，可以在引导指令的标签下缓存问题组信息的编码副本。 所产生的依赖性高速缓存或控制向量高速缓存可以在微处理器流水线的指令发出逻辑阶段的开始时被下一次相应的指令组出现以重新执行。 由于可以在高速缓存中的单个周期中访问编码的问题组位模式，所以具有该实施例的所得微处理器流水线可以被看作是两个并行管道，其中如果存在依赖性高速缓存或控制向量高速缓冲存储器 击中。

    Non-Homogeneous Multi-Processor System With Shared Memory
    4.
    发明申请
    Non-Homogeneous Multi-Processor System With Shared Memory 审中-公开
    具有共享内存的非均匀多处理器系统

    公开(公告)号：US20080162877A1

    公开(公告)日：2008-07-03

    申请号：US12049324

    申请日：2008-03-15

    申请人： Erik Richter Altman ,  Peter George Capek ,  Michael Karl Gschwind ,  Charles Ray Johns ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle ,  Sumedh W. Sathaye ,  John-David Wellman ,  Ravi Nair

    发明人： Erik Richter Altman ,  Peter George Capek ,  Michael Karl Gschwind ,  Charles Ray Johns ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle ,  Sumedh W. Sathaye ,  John-David Wellman ,  Ravi Nair

    IPC分类号： G06F15/76 ,  G06F9/30

    CPC分类号： H04L63/168 ,  H04L67/10

    摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

    摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

    Control signal memoization in a multiple instruction issue microprocessor
    5.
    发明授权
    Control signal memoization in a multiple instruction issue microprocessor 失效
    在多指令发出微处理器中控制信号记忆

    公开(公告)号：US08151092B2

    公开(公告)日：2012-04-03

    申请号：US11034284

    申请日：2005-01-12

    申请人： Erik Richter Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman ,  Victor V. Zyuban

    发明人： Erik Richter Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman ,  Victor V. Zyuban

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3808 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3873

    摘要： A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

    摘要翻译： 在微处理器管线的各个阶段提供动态预测和/或精确缓存机制，使得可以在程序执行过程中存储和存储各种控制信号。 精确的控制信号矢量缓存可以完成。 每当在指令解码，注册重命名和依赖关系检查之后形成问题组时，可以在引导指令的标签下缓存问题组信息的编码副本。 所产生的依赖性高速缓存或控制向量高速缓存可以在微处理器流水线的指令发出逻辑阶段的开始时被下一次相应的指令组出现以重新执行。 由于可以在高速缓存中的单个周期中访问编码的问题组位模式，所以具有该实施例的所得微处理器流水线可以被看作是两个并行的管道，其中如果存在依赖性高速缓存或控制向量高速缓存 击中。