公开(公告)号：US07076681B2

公开(公告)日：2006-07-11

申请号：US10187698

申请日：2002-07-02

Applicant: Pradip Bose ,  Daniel M. Citron ,  Peter W. Cook ,  Philip G. Emma ,  Hans M. Jacobson ,  Prabhakar N. Kudva ,  Stanley E. Schuster ,  Jude A. Rivers ,  Victor V. Zyuban

Inventor： Pradip Bose ,  Daniel M. Citron ,  Peter W. Cook ,  Philip G. Emma ,  Hans M. Jacobson ,  Prabhakar N. Kudva ,  Stanley E. Schuster ,  Jude A. Rivers ,  Victor V. Zyuban

IPC: G06F1/04

CPC classification number: G06F9/3869 ,  G06F1/04 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30083 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3867 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171

Abstract: A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.

Abstract translation: 同步集成电路，如标量处理器或超标量处理器。 电路组件或单元由公共系统时钟计时并同步。 至少两个时钟单元包括多个寄存器级，例如流水线级。 每个时钟单元中的本地时钟发生器将来自一个或多个其他单元的公共系统时钟和失速状态相结合，以调整寄存器时钟频率向上或向下。

公开(公告)号：US06990509B2

公开(公告)日：2006-01-24

申请号：US10093973

申请日：2002-03-08

Applicant: Erdem Hokenek ,  Eko Lisuwandi ,  David Meltzer ,  Mayan Moudgill ,  Victor V. Zyuban

Inventor： Erdem Hokenek ,  Eko Lisuwandi ,  David Meltzer ,  Mayan Moudgill ,  Victor V. Zyuban

IPC: G06F7/50

CPC classification number: G06F7/501

Abstract: An ultra low power adder with sum synchronization which provides a power reduction method in the binary carry propagate adders by using a carry skip technique. The invention eliminates glitches at the adder outputs by preventing signal transitions at the sum outputs until the corresponding carry signals have reached their final values, which is achieved by adding a synchronization circuitry to the sum calculation path.

公开(公告)号：US20120144166A1

公开(公告)日：2012-06-07

申请号：US13371181

申请日：2012-02-10

Applicant: Erik Richter Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman ,  Victor V. Zyuban

Inventor： Erik Richter Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman ,  Victor V. Zyuban

IPC: G06F9/38 ,  G06F9/312

CPC classification number: G06F9/3808 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3873

Abstract: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

Abstract translation: 在微处理器管线的各个阶段提供动态预测和/或精确缓存机制，使得可以在程序执行过程中存储和存储各种控制信号。 精确的控制信号矢量缓存可以完成。 每当在指令解码，注册重命名和依赖关系检查之后形成问题组时，可以在引导指令的标签下缓存问题组信息的编码副本。 所产生的依赖性高速缓存或控制向量高速缓存可以在微处理器流水线的指令发出逻辑阶段的开始时被下一次相应的指令组出现以重新执行。 由于可以在高速缓存中的单个周期中访问编码的问题组位模式，所以具有该实施例的所得微处理器流水线可以被看作是两个并行管道，其中如果存在依赖性高速缓存或控制向量高速缓冲存储器 击中。

公开(公告)号：US08589662B2

公开(公告)日：2013-11-19

申请号：US13371181

申请日：2012-02-10

Applicant: Erik R. Altman ,  Michael K. Gschwind ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman ,  Victor V. Zyuban

Inventor： Erik R. Altman ,  Michael K. Gschwind ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman ,  Victor V. Zyuban

IPC: G06F9/30

CPC classification number: G06F9/3808 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3873

Abstract: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

Abstract translation: 在微处理器管线的各个阶段提供动态预测和/或精确缓存机制，使得可以在程序执行过程中存储和存储各种控制信号。 精确的控制信号矢量缓存可以完成。 每当在指令解码，注册重命名和依赖关系检查之后形成问题组时，可以在引导指令的标签下缓存问题组信息的编码副本。 所产生的依赖性高速缓存或控制向量高速缓存可以在微处理器流水线的指令发出逻辑阶段的开始时被下一次相应的指令组出现以重新执行。 由于可以在高速缓存中的单个周期中访问编码的问题组位模式，所以具有该实施例的所得微处理器流水线可以被看作是两个并行的管道，其中如果存在依赖性高速缓存或控制向量高速缓存 击中。

公开(公告)号：US08151092B2

公开(公告)日：2012-04-03

申请号：US11034284

申请日：2005-01-12

Applicant: Erik Richter Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman ,  Victor V. Zyuban

Inventor： Erik Richter Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman ,  Victor V. Zyuban

IPC: G06F9/30

CPC classification number: G06F9/3808 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3873

Abstract: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

Abstract translation: 在微处理器管线的各个阶段提供动态预测和/或精确缓存机制，使得可以在程序执行过程中存储和存储各种控制信号。 精确的控制信号矢量缓存可以完成。 每当在指令解码，注册重命名和依赖关系检查之后形成问题组时，可以在引导指令的标签下缓存问题组信息的编码副本。 所产生的依赖性高速缓存或控制向量高速缓存可以在微处理器流水线的指令发出逻辑阶段的开始时被下一次相应的指令组出现以重新执行。 由于可以在高速缓存中的单个周期中访问编码的问题组位模式，所以具有该实施例的所得微处理器流水线可以被看作是两个并行的管道，其中如果存在依赖性高速缓存或控制向量高速缓存 击中。