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公开(公告)号：US4432050A
公开(公告)日：1984-02-14
申请号：US192875
申请日：1980-10-01
CPC分类号： G06F9/24
摘要： Use of a control storage device coupled with a central processing unit is locked, during the loading process from the unit to the device, to a would-be user of the device until such loading process is complete as indicated by a so-called "unlock" command received from the central processing unit. An indication of an error or malfunction in the control storage device either during the loading process or thereafter is also provided to the central processing unit.
摘要翻译： 在从单元到设备的装载过程中，与中央处理单元耦合的控制存储设备的使用被锁定，直到这种加载过程完成为止，如所谓的“解锁 “命令从中央处理单元收到。 控制存储设备中的错误或故障的指示在加载过程中或之后也被提供给中央处理单元。
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2.发明授权Transfer control technique between two units included in a data processing system 失效包括在数据处理系统中的两个单元之间的传输控制技术
公开(公告)号：US4225921A
公开(公告)日：1980-09-30
申请号：US947990
申请日：1978-10-02
CPC分类号： G06F9/226 , G06F13/4239
摘要： A data processing unit's request to a data processing device for the transfer of control and processing of an operation in response to an instruction from the unit, is stalled by the device, dependent on the type of instruction, for a period of time, also dependent on the type of instruction, until the device is ready to process such operation. A shift register arrangement is used in the device, which, dependent on the indicia stored therein, which indicia are appropriately loaded in such register dependent on the type of instruction, is used to delay a response to the unit by requesting the unit to make another request to the device to process the operation called for by the instruction.
摘要翻译： 数据处理单元响应于来自该单元的指令传送控制和处理操作的数据处理设备的请求被设备停止，取决于指令的类型一段时间，也依赖于 对指令的类型，直到设备准备好处理这样的操作。 在设备中使用移位寄存器装置，其根据存储在其中的标记，根据指令的类型将哪个标记适当地加载在这样的寄存器中，用于通过请求单元进行另一个来延迟对单元的响应 请求设备处理由指令调用的操作。
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公开(公告)号：US4396981A
公开(公告)日：1983-08-02
申请号：US191445
申请日：1980-09-29
摘要： A writeable control store in a data processing system is provided with a dual mode capability. Coupled with the control store in the system is a central processing unit which may provide the next address of the control store's memory dependent upon the mode of the control store. Otherwise, also dependent upon such mode, the control store memory is addressed, dependent upon the results of tests conducted in the central processing unit, by one of at least two alternative addresses. The control words addressed in the writeable control store are used to control the operation of the central processing unit.
摘要翻译： 数据处理系统中的可写控制存储器具有双模式能力。 与系统中的控制存储器耦合是中央处理单元，其可以根据控制存储器的模式提供控制存储器的存储器的下一个地址。 否则，还取决于这种模式，取决于在中央处理单元中进行的测试的结果，通过至少两个替代地址之一来寻址控制存储器存储器。 在可写控制存储器中寻址的控制字用于控制中央处理单元的操作。
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公开(公告)号：US4287562A
公开(公告)日：1981-09-01
申请号：US73058
申请日：1979-09-06
申请人： Boyd E. Darden , Henry F. Hartley
发明人： Boyd E. Darden , Henry F. Hartley
CPC分类号： G06F9/4825 , G06F13/12
摘要： A data processing system includes a central processing unit, a main store and device controllers which couple to a bus system. Each controller has a number of device adapter units. One controller includes a real time adapter unit which instead of being connected to control a peripheral device is connected to provide a timer facility for use by the central processing unit in executing tasks. The real time adapter unit includes microprocessing circuits and clock circuits. These circuits are connected to provide accurate and reliable time of day values in response to commands from the central processing unit.
摘要翻译： 数据处理系统包括中央处理单元，主存储器和耦合到总线系统的设备控制器。 每个控制器都有多个设备适配器单元。 一个控制器包括实时适配器单元，而不是连接到控制外围设备的连接器，以提供中央处理单元在执行任务中使用的定时器设备。 实时适配器单元包括微处理电路和时钟电路。 这些电路被连接以响应于来自中央处理单元的命令提供准确和可靠的时间值。
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5.发明授权
公开(公告)号：US4217639A
公开(公告)日：1980-08-12
申请号：US947986
申请日：1978-10-02
摘要： Clock logic for generating multiple clock pulses during a single clock cycle. In response to a signal indicative of a clock cycle, effectively two clock pulses are produced in a relatively short period of time. Such logic, which includes a delay element, causes first a load pulse to be produced thereby enabling the loading of information into, for example, a register. Additionally, and within the same clock cycle as the load pulse and in response to the same signal, an increment pulse is produced to, for example, increment a counting function which may be included in such register.
摘要翻译： 用于在单个时钟周期内产生多个时钟脉冲的时钟逻辑。 响应于指示时钟周期的信号，有效地在相对短的时间段内产生两个时钟脉冲。 包括延迟元件的这种逻辑首先引起负载脉冲的产生，从而使得能够将信息加载到例如寄存器中。 此外，并且在与负载脉冲相同的时钟周期内，并且响应于相同的信号，产生增量脉冲，例如增加可包括在这种寄存器中的计数功能。
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6.发明授权Adapter unit for use in a data processing system for processing a variety of requests 失效用于处理各种请求的数据处理系统中的适配器单元
公开(公告)号：US4295194A
公开(公告)日：1981-10-13
申请号：US73056
申请日：1979-09-06
申请人： Boyd E. Darden , Henry F. Hartley
发明人： Boyd E. Darden , Henry F. Hartley
CPC分类号： G06F9/4825
摘要： A data processing system includes a central processing unit, a main store and device controllers which couple to a bus system. Each controller has a number of device adapter units. One controller includes a real time adapter unit which instead of being connected to control a peripheral device is connected to provide a timer facility for use by the central processing unit (CPU) in executing tasks. The real time adapter unit includes a microprocessing section, a timer section, and a module time of day section. The time of day includes circuits which are connected to provide accurate and reliable time of day values. The timer module section includes circuits which are connected to provide variable time intervals. The circuits of both sections are connected to the circuits of the microprocessing section. In response to a number of different commands received from the central processing unit, the microprocessing unit (MPU) of the microprocessing section loads the various registers included within the timer module section to establish a desired interval at which it is to monitor the time of day operation of the time of day section. When the microprocessing unit establishes that the particular time of day operation specified by the central processing unit has been completed, it generates signals for notifying the central processing unit.
摘要翻译： 数据处理系统包括中央处理单元，主存储器和耦合到总线系统的设备控制器。 每个控制器都有多个设备适配器单元。 一个控制器包括实时适配器单元，而不是连接到控制外围设备的连接器，以提供定时器设施供中央处理单元（CPU）执行任务使用。 实时适配器单元包括微处理部分，定时器部分和模块时间段。 一天中的时间包括连接到提供准确和可靠的时间值的电路。 定时器模块部分包括连接以提供可变时间间隔的电路。 两部分的电路连接到微处理部分的电路。 响应于从中央处理单元接收到的多个不同的命令，微处理部分的微处理单元（MPU）加载包括在定时器模块部分内的各种寄存器，以建立期望监视时间的间隔 时间段操作。 当微处理单元确定由中央处理单元指定的特定时间操作已经完成时，它产生用于通知中央处理单元的信号。
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公开(公告)号：US4316246A
公开(公告)日：1982-02-16
申请号：US73057
申请日：1979-09-06
摘要： An adapter includes free running low power clock circuits connected to provide a time of day value accessible by a central processing unit which couples to the adapter through a controller subsystem. The adapter cicuits are constructed on a circuit board which is installed as part of the controller subsystem. The clock circuits are connected to one terminal of a battery power supply whose other terminal connects to an interface connector included within the adapter. Upon installing the adapter board in the subsystem, the battery power supply is connected to provide power for operating the clock circuits. When the adapter is removed from the subsystem, the battery power supply is disconnected, preventing it from discharging. The adapter includes an adapter connector for connecting the output terminal of the battery power supply to enable the battery to be charged or its power level monitored when the adapter circuit board is installed.
摘要翻译： 适配器包括自由运行的低功率时钟电路，其连接以提供通过控制器子系统耦合到适配器的中央处理单元可访问的时间值。 适配器电路构造在作为控制器子系统的一部分安装的电路板上。 时钟电路连接到电池电源的一个端子，其另一个端子连接到包含在适配器内的接口连接器。 将适配器板安装在子系统中后，连接电池电源，为操作时钟电路提供电源。 当适配器从子系统中取出时，电池电源断开，防止电池放电。 适配器包括用于连接电池电源的输出端子的适配器连接器，以便在安装适配器电路板时对电池进行充电或监视其功率电平。
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