公开(公告)号：US5900020A

公开(公告)日：1999-05-04

申请号：US678372

申请日：1996-06-27

申请人： Robert J. Safranek ,  Thomas D. Lovett ,  Robert T. Joersz ,  Bruce M. Gilbert

发明人： Robert J. Safranek ,  Thomas D. Lovett ,  Robert T. Joersz ,  Bruce M. Gilbert

IPC分类号： G06F12/08 ,  G06F13/14 ,  G06F13/24 ,  G06F13/42

CPC分类号： G06F12/0828 ,  G06F12/0813 ,  G06F2212/2542

摘要： A method and apparatus for maintaining processor consistency in a multiprocessor computer such as a multinode computer system are disclosed. A processor proceeds with write operations before its previous write operations complete, while processor consistency is maintained. A write operation begins with a request by the processor to invalidate copies of the data stored in other nodes. This current invalidate request is queued while acknowledging to the processor that the request is complete even though it has not actually completed. The processor proceeds to complete the write operation by changing the data. It can then execute subsequent operations, including other write operations. The queued request, however, is not transmitted to other nodes in the computer until all previous invalidate requests by the processor are complete. This ensures that the current invalidate request will not pass a previous invalidate request. The invalidate requests are added and removed from a processor's outstanding invalidate list as they arise and are completed. An invalidate request is completed by notifying the nodes in a linked list related to the current invalidate request that data shared by the node is now invalid.

摘要翻译： 公开了一种在诸如多节点计算机系统的多处理器计算机中维持处理器一致性的方法和装置。 处理器在其先前的写入操作完成之前进行写入操作，同时保持处理器的一致性。 写入操作从处理器的请求开始，使存储在其他节点中的数据的副本无效。 该当前无效请求被排队，同时向处理器确认请求完成，即使它尚未实际完成。 处理器继续通过更改数据来完成写入操作。 然后，它可以执行后续操作，包括其他写入操作。 然而，排队的请求不会传输到计算机中的其他节点，直到处理器的所有先前的无效请求都完成为止。 这确保当前的无效请求不会通过先前的无效请求。 无效请求在处理器未完成的无效列表出现并被完成时被添加和删除。 通过通知与当前无效请求相关的链接列表中的节点，节点共享的数据现在无效，则完成无效请求。

公开(公告)号：US06041376A

公开(公告)日：2000-03-21

申请号：US850736

申请日：1997-04-24

申请人： Bruce Michael Gilbert ,  Robert T. Joersz ,  Thomas D. Lovett ,  Robert J. Safranek

发明人： Bruce Michael Gilbert ,  Robert T. Joersz ,  Thomas D. Lovett ,  Robert J. Safranek

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/364

CPC分类号： G06F12/0815 ,  G06F13/1663 ,  G06F12/0813

摘要： A multiprocessor system that assures forward progress of local processor requests for data by preventing other nodes from accessing the data until the processor request is satisfied. In one aspect of the invention, the local processor requests data through a remote cache interconnect. The remote cache interconnect tells the local processor to retry its request for data at a later time, so that the remote cache interconnect has sufficient time to obtain the data from the system interconnect. When the remote cache interconnect receives the data from the system interconnect, a hold flag is set. Any requests from other nodes for the data are rejected while the hold flag is set. When the local processor issues a retry request, the data is delivered to the processor and the hold flag is cleared. Other nodes may then obtain control of the data.

摘要翻译： 一种多处理器系统，通过防止其他节点访问数据直到满足处理器请求，确保本地处理器对数据的请求的正向进展。 在本发明的一个方面，本地处理器通过远程高速缓存互连来请求数据。 远程缓存互连告诉本地处理器稍后重试其对数据的请求，使得远程高速缓存互连具有足够的时间从系统互连获取数据。 当远程缓存互连从系统互连接收数据时，设置保持标志。 来自其他节点的任何数据请求将在保持标志置1时被拒绝。 当本地处理器发出重试请求时，数据被传递给处理器，并且保持标志被清除。 其他节点可以获得数据的控制。