公开(公告)号：US5625325A

公开(公告)日：1997-04-29

申请号：US577780

申请日：1995-12-22

申请人： Robert R. Rotzoll ,  Jaideep Prakash

发明人： Robert R. Rotzoll ,  Jaideep Prakash

IPC分类号： H03L7/089 ,  H03L7/093 ,  H03L7/099

CPC分类号： H03L7/0898 ,  H03L7/099 ,  H03J2200/10 ,  H03L2207/05 ,  H03L7/093

摘要： The system and method for phase lock loop (PLL) gain stabilization uses a digital compensation technique to correct for the large amount of gain variation present in a voltage controlled oscillator (VCO) utilizing a varactor diode. AVCO is arranged with additional capacitance in parallel with the vatactor diode of the VCO. By using multiple capacitors, more or less capacitance can be switched into parallel with the vatactor diode. Gain variation is accomplished by switching capacitors into the circuit, and for each combination of capacitors used in the resonant inductance-capacitance (LC) circuit of the VCO, the gain of the phase detector in the PLL is adjusted simultaneously. The phase detector has a charge pump that drives a current into a loop filter having a capacitor with a fixed value. The gain adjustment is accomplished by varying the amount of current available from the charge pump to this filter capacitor. The gain compensation circuit that generates this charge pump current takes the same digital code used to control the capacitors in the VCO as an input and performs a digital-to-analog conversion in current mode. The analog current is then transformed into a second-order polynomial via a current squarer and programmable current scalers to provide a gain compensation signal for the phase detector. The programmable current scalers determine the coefficients of the second order polynomial. Therefore, for any given VCO characteristic with regard to the additional capacitors and the varactor diode, the coefficients of the current scalers can be adjusted to accommodate a more precise PLL gain control.

摘要翻译： 用于锁相环（PLL）增益稳定的系统和方法使用数字补偿技术来校正利用变容二极管的压控振荡器（VCO）中存在的大量增益变化。 AVCO与VCO的Vatactor二极管并联设置附加电容。 通过使用多个电容器，可以将或多或少的电容转换成与电抗器二极管并联。 通过将电容器切换到电路中来实现增益变化，并且对于在VCO的谐振电感 - 电容（LC）电路中使用的电容器的每个组合，PLL中的相位检测器的增益被同时调整。 相位检测器具有将电流驱动到具有固定值的电容器的环路滤波器中的电荷泵。 通过改变从电荷泵到该滤波电容器的可用电流量来实现增益调节。 产生该电荷泵电流的增益补偿电路采用与用于控制VCO中的电容器相同的数字代码作为输入，并在当前模式下执行数模转换。 然后通过电流平方和可编程电流定标器将模拟电流转换成二阶多项式，以为相位检测器提供增益补偿信号。 可编程电流定标器确定二阶多项式的系数。 因此，对于关于附加电容器和变容二极管的任何给定的VCO特性，可以调整电流定标器的系数以适应更精确的PLL增益控制。

公开(公告)号：US07145928B1

公开(公告)日：2006-12-05

申请号：US10642774

申请日：2003-08-18

申请人： Adrian Maxim ,  Jaideep Prakash

发明人： Adrian Maxim ,  Jaideep Prakash

IPC分类号： H01S3/00

CPC分类号： H01S5/042 ,  G02F1/0123 ,  H01S5/0427 ,  H03K25/12

摘要： High frequency laser diode (LD) and electro-absorption modulator (EAM) integrated circuit drivers using a cascaded output switch architecture that increases the output current and voltage edge speed and reduces the peaking and ringing of the output waveform, thus improving the deterministic jitter performance. Also disclosed is a method and apparatus that provides a modulation current dependence of both turn-on and turn-off driving currents that lead to an optimal compromise between the edge speed and output overshoot for a wide range of modulation currents. A PTAT temperature dependence of both voltage swing and current level in the predriver assures a low variation of the overshoot and rise/fall time over a wide temperature range. Using the cascaded output switch architecture provides an easy way of on-chip summation of the modulation and bias currents. Biasing the cascode device with a supply and modulation current dependent base voltage provides an optimum headroom output switch.

摘要翻译： 使用级联输出开关架构的高频激光二极管（LD）和电吸收调制器（EAM）集成电路驱动器，可增加输出电流和电压边沿速度，并减少输出波形的峰值和振铃，从而提高确定性抖动性能 。 还公开了一种提供导通和截止驱动电流的调制电流依赖性的方法和装置，其导致宽范围调制电流的边沿速度和输出过冲之间的最佳折中。 在预驱动器中，电压摆幅和电流电平的PTAT温度依赖性确保了在宽温度范围内的过冲变化和上升/下降时间的低变化。 使用级联输出开关架构提供了调制和偏置电流的片上求和的简单方法。 使用电源和调制电流依赖的基极电压来偏置共源共栅器件可提供最佳的净空输出开关。

公开(公告)号：US06385265B1

公开(公告)日：2002-05-07

申请号：US09128901

申请日：1998-08-04

申请人： Michael L. Duffy ,  Bertrand J. Williams ,  Phillip J. Kruczkowski ,  Jaideep Prakash ,  Nathan Y. Moyal

发明人： Michael L. Duffy ,  Bertrand J. Williams ,  Phillip J. Kruczkowski ,  Jaideep Prakash ,  Nathan Y. Moyal

IPC分类号： H03D324

CPC分类号： H03L7/0893 ,  H03L7/0896

摘要： A circuit and method comprising a charge pump having a first and a second differential element. The charge pump may be configured to generate a first and a second output signal in response to the first and second differential elements. The first differential element may comprise (i) a first unity gain buffer and (ii) a first and a second transistor pair configured to receive a first and second control signal. The second differential element may comprise (i) a second unity gain buffer and (ii) a third and a fourth transistor pair configured to receive the first and second control signals. The first and second unity gain buffers may stabilize the source nodes of each of the transistors pairs.

摘要翻译： 一种电路和方法，包括具有第一和第二差分元件的电荷泵。 电荷泵可以被配置为响应于第一和第二差分元件而产生第一和第二输出信号。 第一差分元件可以包括（i）第一单位增益缓冲器和（ii）被配置为接收第一和第二控制信号的第一和第二晶体管对。 第二差分元件可以包括（i）第二单位增益缓冲器和（ii）被配置为接收第一和第二控制信号的第三和第四晶体管对。 第一和第二单位增益缓冲器可以稳定每个晶体管对的源节点。

公开(公告)号：US5490171A

公开(公告)日：1996-02-06

申请号：US208603

申请日：1994-03-09

申请人： Phillip R. Epley ,  Charles R. Hoffman ,  Jaideep Prakash

发明人： Phillip R. Epley ,  Charles R. Hoffman ,  Jaideep Prakash

IPC分类号： H03K19/0175 ,  H01L27/02 ,  H02H9/04 ,  H03K17/687 ,  H03K19/0944 ,  H04L25/02 ,  H04B3/00 ,  H04B1/38

CPC分类号： H01L27/0255 ,  H02H9/046

摘要： A single-port network node transceiver that does not draw any substantial current from the network when it is powered-down, enabling it to meet the ISDN powered-down loading specification when built on a CMOS integrated circuit chip. The pull-up transistors of the transmitter output circuit each have means for shorting the well terminal to source terminal connection when the circuit is operating and opening the connection when the power to the transceiver is shut down. The opening of this connection prevents the well-substrate junction of the pull-up transistors from becoming forward biased and drawing current from the network when the power to the transceiver is off and there is voltage present on the network. The transceiver also includes a plurality of ESD overvoltage protection diodes in series between the power supply rail and each input/output terminal. Since multiple diodes are connected in series and their voltage drops are added together, the diodes also do not draw current from the network when the transceiver is powered down.

摘要翻译： 单端口网络节点收发器在掉电时不会从网络中获取任何实质的电流，使其能够在内置CMOS集成电路芯片时满足ISDN掉电负载规范。 发射机输出电路的上拉晶体管各自具有用于当电路正在操作时将阱端子短路到源极端子连接的装置，并且当收发器的电源被关闭时打开连接的装置。 当连接到收发器的电源关闭并且网络上存在电压时，这种连接的打开可以防止上拉晶体管的良好的衬底结点向前偏置并从网络中抽出电流。 收发器还包括串联在电源轨和每个输入/输出端之间的多个ESD过压保护二极管。 由于多个二极管串联连接并且它们的电压降被加在一起，所以当收发器掉电时，二极管也不会从网络中抽出电流。

公开(公告)号：US5748127A

公开(公告)日：1998-05-05

申请号：US579073

申请日：1995-12-22

申请人： Jaideep Prakash ,  John Paul Norsworthy ,  Bruce Andrew Doyle

发明人： Jaideep Prakash ,  John Paul Norsworthy ,  Bruce Andrew Doyle

IPC分类号： H03M1/06 ,  H03M1/74 ,  H03M1/66

CPC分类号： H03M1/0604 ,  H03M1/742

摘要： A precise current cell for a digital-to-analog (D/A) convertor circuit is designed to compensate for manufacturing process variations. The cell uses a cascoded transistor chain to control the output voltage and isolate voltage supply noise. An external (off-chip) bias current is fed into a cascoded biasing string of eight transistors, which are further mirrored to the current cell itself. The biasing scheme accounts for manufacturing process variations in the chip, which leads to very precise current being replicated at the output of the D/A circuit. Current steering and an improved shunt path within the current cell minimizes voltage swings during switching of the current cell. This allows for faster switching of the cell while minimizing noise coupling due to the voltage swings. The current cell also has an associated biasing stage. This biasing stage allows for improved matching within the current cell, resulting in improved accuracy of conversion. Additionally, the biasing circuit minimizes noise coupling from ground potential to the D/A convertor output. A reset circuit is also included. This current cell, associated biasing stage, and reset circuit is suitable for applications requirement precise D/A conversions at high speeds.

摘要翻译： 用于数模（D / A）转换器电路的精确电流单元被设计为补偿制造工艺变化。 电池使用级联晶体管链来控制输出电压并隔离电源电压噪声。 外部（芯片外）偏置电流被馈送到八个晶体管的级联偏压串中，其进一步镜像到当前单元本身。 偏置方案考虑到芯片中的制造工艺变化，这导致在D / A电路的输出端复制非常精确的电流。 当前电池中的电流转向和改善的分流路径使当前电池切换期间的电压摆幅最小化。 这允许更快地切换电池，同时最小化由于电压摆动引起的噪声耦合。 当前单元还具有相关联的偏置级。 该偏置级允许改善当前单元内的匹配，从而提高转换精度。 此外，偏置电路最小化从地电位到D / A转换器输出的噪声耦合。 还包括复位电路。 该电流单元，相关偏置级和复位电路适用于要求高速精确D / A转换的应用。

公开(公告)号：US5717730A

公开(公告)日：1998-02-10

申请号：US577653

申请日：1995-12-22

申请人： Jaideep Prakash ,  Robert Rudolf Rotzoll

发明人： Jaideep Prakash ,  Robert Rudolf Rotzoll

IPC分类号： H03L7/185 ,  H03L7/23 ,  H03D3/24

CPC分类号： H03L7/23 ,  H03L7/185

摘要： A monolithic device is shown having a number of phase locked loops (PLLs) constructed thereon. At least one of the PLLs is constructed as a multiple loop having an output of one PLL loop tied back to the feedback path of the other loop of the pair. In this manner, tight resolution can be obtained in one loop while the bandwidth of that loop is coarse. The bandwidth of the second loop is tight, thereby giving good resolution to the first loop while still avoiding the problems inherent with noise injection locking from other PLLs on the same device.

摘要翻译： 示出了在其上构造有多个锁相环（PLL）的单片器件。 PLL中的至少一个被构造为具有一个PLL环路的输出绑定回到该对的另一个环路的反馈路径的多环路。 以这种方式，可以在一个环路中获得紧密的分辨率，而该环路的带宽是粗糙的。 第二个环路的带宽很紧，从而为第一个环路提供了良好的分辨率，同时仍然避免了同一设备上其他PLL噪声注入锁定所固有的问题。

公开(公告)号：US5648744A

公开(公告)日：1997-07-15

申请号：US579069

申请日：1995-12-22

申请人： Jaideep Prakash ,  Robert Rudolf Rotzoll

发明人： Jaideep Prakash ,  Robert Rudolf Rotzoll

IPC分类号： H03L7/089 ,  H03L7/099 ,  H03L7/10

CPC分类号： H03L7/099 ,  H03L7/10 ,  H03L7/0891

摘要： A system and method for establishing the frequency of a voltage controlled oscillator ("VCO") within narrowly defined frequency bands. The resonant circuit of the VCO uses selectable elements, such as varactor diodes, to establish the operating frequency band. The control voltage of the VCO is varied within a voltage range to adjust the VCO output frequency. A phase detector compares the VCO output to a reference signal. If the phase detector determines that there is an imbalance between the VCO output and the reference signal, then it produces a signal which indicates whether the VCO frequency should be increased or decreased to match the reference signal frequency. If the control voltage is outside of the voltage range, then the system allows the operating frequency band to be changed by varying the number of selectable elements in response to the phase detector signal.

摘要翻译： 用于在窄定义频带内建立压控振荡器（“VCO”）的频率的系统和方法。 VCO的谐振电路使用可变元件，例如变容二极管来建立工作频带。 VCO的控制电压在电压范围内变化，以调整VCO的输出频率。 相位检测器将VCO输出与参考信号进行比较。 如果相位检测器确定VCO输出和参考信号之间存在不平衡，则产生一个信号，该信号指示VCO频率是应当增加还是降低以匹配参考信号频率。 如果控制电压超出电压范围，则系统允许通过根据相位检测器信号改变可选元件的数量来改变工作频带。