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公开(公告)号：US08818361B2
公开(公告)日：2014-08-26
申请号：US13070550
申请日：2011-03-24
申请人： Robert Skog , Bo Astrom , Tomas Holm , Lars-Orjan Kling
发明人： Robert Skog , Bo Astrom , Tomas Holm , Lars-Orjan Kling
IPC分类号： H04W4/00
摘要： Method and arrangement for supporting connectivity of a wireless device to a network infrastructure. An infrastructure provider associates a set of device identification numbers to a first radio access provider in a subscription database of the infrastructure provider. The infrastructure provider also sets the first radio access provider as a preferred roaming partner in a SIM that comprises a subscriber identifier with a network identifier of the infrastructure provider. The SIM is provided for use in the device, to enable access to the network infrastructure over a radio access network of the first radio access provider based on the subscriber identifier and the preferred roaming partner in the SIM.
摘要翻译： 支持无线设备到网络基础设施的连接的方法和装置。 基础设施提供商将一组设备标识号与基础架构提供商的订阅数据库中的第一无线电接入提供商相关联。 基础设施提供商还将第一无线电接入提供商设置为SIM中的首选漫游伙伴，其包括具有基础设施提供商的网络标识符的订户标识符。 SIM被提供用于该设备中，以便基于SIM中的用户标识符和优选的漫游伙伴，使得能够通过第一无线电接入提供商的无线电接入网络访问网络基础设施。
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2.发明授权公开(公告)号：US07197622B2
公开(公告)日：2007-03-27
申请号：US10450827
申请日：2001-12-12
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , H04L29/06 , H04L45/00 , H04L45/745 , H04L69/04 , H04L69/16 , H04L69/161 , H04L69/22
摘要： Signal elements are mapped to a limited range of identifiers by emulating a “virtual” space of identifiers larger than the real limited space of identifiers. The larger virtual identifier space is implemented by an intermediate memory, which provides storage of identifiers assigned from the real space of identifiers. For each signal element to be mapped to an identifier, the intermediate memory is addressed by a hash value calculated from at least part of the signal element, thus allowing access to an identifier. The larger virtual space gives a better distribution of signal elements to the identifiers; and reduces the probability of different signal elements being mapped to the same identifier (“clashing”). For an efficient reduction of the clashing probability, identifiers with a low probability of being active are assigned to the intermediate memory to represent new signal elements.
摘要翻译： 信号元素通过仿真大于标识符的实际有限空间的标识符的“虚拟”空间来映射到有限范围的标识符。 较大的虚拟标识符空间由中间存储器实现，其提供从标识符的真实空间分配的标识符的存储。 对于要映射到标识符的每个信号元素，通过从信号元素的至少一部分计算的散列值寻址中间存储器，从而允许访问标识符。 更大的虚拟空间给信号元素更好地分配给标识符; 并且降低将不同信号元素映射到相同标识符（“冲突”）的概率。 为了有效降低冲突概率，将具有低活动概率的标识符分配给中间存储器以表示新的信号元素。
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3.发明授权Method and device to execute two instruction sequences in an order determined in advance 失效以预先确定的顺序执行两个指令序列的方法和装置
公开(公告)号：US4985826A
公开(公告)日：1991-01-15
申请号：US192512
申请日：1988-05-10
CPC分类号： G06F9/3851 , G06F9/3834 , G06F9/3861
摘要： A data processing system executes two instruction sequences in an order determined in advance. Each sequence is stored in a separate memory. Data information used in the second sequence is not guaranteed to be independent of data information used in the first sequence. Increased data handling capacity is achieved in the following manner: both sequences are initially executed in parallel. An address included in a read instruction associated with the second sequence is intermediately stored in an auxiliary memory if it has not been previously selected in conjunction with a write instruction of the second sequence. The intermediately stored address is compared with the write addresses of the first sequence and execution of the second sequence is restarted upon detection of a match.
摘要翻译： PCT No.PCT / SE87 / 00438 Sec。 371日期：1988年5月10日 102（e）日期1988年5月10日PCT提交1987年9月28日PCT公布。 第WO88 / 02514号公报 日期：1988年4月7日。数据处理系统按照预先确定的顺序执行两个指令序列。 每个序列都存储在一个单独的存储器中。 在第二序列中使用的数据信息不能保证与第一序列中使用的数据信息无关。 以下列方式实现增加的数据处理能力：两个序列最初并行执行。 包括在与第二序列相关联的读取指令中的地址如果没有先前与第二序列的写入指令一起选择，则将其中间存储在辅助存储器中。 将中间存储的地址与第一序列的写入地址进行比较，并且在检测到匹配时重新启动第二序列的执行。
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公开(公告)号：US20090199266A1
公开(公告)日：2009-08-06
申请号：US12158791
申请日：2005-12-30
申请人： Lars-Orjan Kling , Robert E. Penny , Yonghui Jin
发明人： Lars-Orjan Kling , Robert E. Penny , Yonghui Jin
CPC分类号： H04L63/0263 , H04L63/101
摘要： A method and compiler for compiling hierarchical command based policy rules to a flat filter list structure adapted for storage in a Content Addressable Memory (CAM), wherein the policy rules are organized in a tree-structure of classifiers. First, all of the possible search paths in the tree structure are found, and then only the valid search paths according to defined criteria are added to the flat filter list. The CAM may be a Ternary Content Addressed Memory.
摘要翻译： 一种用于将基于分级命令的策略规则编译成适于在内容可寻址存储器（CAM）中存储的平坦过滤器列表结构的方法和编译器，其中所述策略规则被组织在分类器的树结构中。 首先，找到树结构中的所有可能的搜索路径，然后根据定义的标准将仅有的搜索路径添加到平坦过滤器列表中。 CAM可以是三进制内容寻址存储器。
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公开(公告)号：US07369562B2
公开(公告)日：2008-05-06
申请号：US10433122
申请日：2000-11-29
申请人： Johan Johansson , Lars-Orjan Kling , Ake Lindholm
发明人： Johan Johansson , Lars-Orjan Kling , Ake Lindholm
IPC分类号： H04L12/56
CPC分类号： H04L45/60 , H04L29/06 , H04L29/12009 , H04L29/12018 , H04L29/12924 , H04L45/00 , H04L47/10 , H04L47/125 , H04L49/602 , H04L61/10 , H04L61/6063 , H04L69/08 , H04L69/12 , H04L69/40 , H04Q3/0045
摘要： The present invention relates to a telecommunications node (1a) that is able to handle IP-traffic and to terminate telecommunications traffic, which node includes means for simple and effective load distribution between resources (40-43) in the node. The inventive telecommunications node (1a) includes board internal IP-subnets (45, 46) with associated subnet interfaces (45a, 46a) having interface addresses and a distributed forwarding engine structure where every device board (10, 11a, 12a) associated with the handling of IP-traffic is provided with a forwarding engine (20-22). Each board internal IP-subnet (45, 46) is associated with at least one predetermined node resource (40-43) for processing telecommunications traffic, thereby enabling a resource manager (49) to perform load distribution by ordering a destination address for a selected stream of IP-traffic, which is to terminate in the node, to be based on the interface address associated with a selected board internal IP-subnet (45, 46).
摘要翻译： 本发明涉及能够处理IP业务并终止电信业务的电信节点（1a），该节点包括用于节点中的资源（40-43）之间的简单而有效的负载分配的装置。 本发明的电信节点（1a）包括具有相关子网接口（45a，46a）的板内部IP子网（45,46），其具有接口地址和分布式转发引擎结构，其中每个设备板（10,11a，12） a）与转发引擎（20-22）一起提供与IP流量的处理相关联。 每个板内部IP子网（45,46）与至少一个用于处理电信业务的预定节点资源（40-43）相关联，从而使得资源管理器49可以通过排序所选择的目标地址来执行负载分配 基于与所选择的板内部IP子网（45,46）相关联的接口地址，终止在节点中的IP流量流。
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6.发明授权Method and device to execute two instruction sequences in an order determined in advance 失效以预先确定的顺序执行两个指令序列的方法和装置
公开(公告)号：US4956770A
公开(公告)日：1990-09-11
申请号：US197410
申请日：1988-05-17
申请人： Sten E. Johnson , Lars-Orjan Kling
发明人： Sten E. Johnson , Lars-Orjan Kling
IPC分类号： G06F20060101 , G06F9/30 , G06F9/38 , G06F13/10 , G06F15/16 , G06F15/177
CPC分类号： G06F9/3889 , G06F9/3834
摘要： A data processing system which executes two instruction sequences in an order determined in advance. With the aid of instructions, a main memory common to both sequences is activated for data information reading/writing. Increased data handling capacity is achieved in the following manner: both sequences are executed in parallel to start with. During execution of the first sequence, the main memory is prevented from being activated for writing due to the second sequence write instructions. A write address and data information included in a write instruction associated with the second sequence are intermediately stored. The intermediately stored write address is compared with the read addresses of the second sequence, and data information is prevented from being read from the main memory in response to an identity of the addresses, the intermediately stored data information being read instead. An address included in a read instruction associated with the second sequence is intermediately stored if this address has not been previously selected in conjuction with a write instruction associated with the second sequence. The intermediately stored read address is compared with the write address of the first sequence and execution of the second sequence is restarted in response to an identity of the addresses.
摘要翻译： PCT No.PCT / SE87 / 00437 Sec。 371日期1988年5月17日 102（e）日期1988年5月17日PCT提交1987年9月28日PCT公布。 出版物WO88 / 02513 日期：1988年4月7日。一种数据处理系统，其以预先确定的顺序执行两个指令序列。 借助于指令，两个序列共同的主存储器被激活用于数据信息读/写。 以下列方式实现数据处理能力的提高：两个序列并行执行。 在第一序列的执行期间，由于第二次写入指令，防止主存储器被激活以进行写入。 包括在与第二序列相关联的写入指令中的写入地址和数据信息被中间存储。 中间存储的写入地址与第二序列的读取地址进行比较，并且响应于地址的身份防止数据信息被从主存储器读取，中间存储的数据信息被改为读取。 如果该地址未被预先与与第二序列相关联的写入指令选择，则包含在与第二序列相关联的读取指令中的地址被中间存储。 中间存储的读地址与第一序列的写地址进行比较，并且响应于地址的标识重新启动第二序列的执行。
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