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    Integrated circuit capacitor
    1.
    发明授权
    Integrated circuit capacitor 有权

    公开(公告)号：US06653676B2

    公开(公告)日：2003-11-25

    申请号：US09918228

    申请日：2001-07-30

    申请人： Robert Tsu ,  Isamu Asano ,  Shinpei Iijima ,  William R. McKee

    发明人： Robert Tsu ,  Isamu Asano ,  Shinpei Iijima ,  William R. McKee

    IPC分类号： H01L27108

    CPC分类号： H01L28/75 ,  H01L21/28518 ,  H01L21/76897 ,  H01L28/55 ,  H01L28/90

    摘要： The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.

    Integrated circuit capacitor
    2.
    发明授权
    Integrated circuit capacitor 失效
    集成电路电容

    公开(公告)号：US06294420B1

    公开(公告)日：2001-09-25

    申请号：US09014724

    申请日：1998-01-28

    申请人： Robert Tsu ,  Isamu Asano ,  Shinpei Iijima ,  William R. McKee

    发明人： Robert Tsu ,  Isamu Asano ,  Shinpei Iijima ,  William R. McKee

    IPC分类号： H01L218242

    CPC分类号： H01L28/75 ,  H01L21/28518 ,  H01L21/76897 ,  H01L28/55 ,  H01L28/90

    摘要： The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.

    摘要翻译： 本发明公开了一种新颖的集成电路电容器及其形成方法。 电容器形成从邻近绝缘区域26的基极18开始。该基极18可以包括多晶硅或金属。 诸如硅化金属的第一材料的层28形成在基极电极18上以及相邻的绝缘区域上。 然后可以通过使第一材料28与基底电极18反应并从绝缘区域26去除第一材料28的未反应部分来形成自对准电容器电极12.然后通过在电容器电极12上形成介电层16来完成电容器 自对准电容器电极12和在电介质层16上的第二电容器电极14。

    Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer
    4.
    发明授权
    Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer 有权
    使用用于低介电常数层间和层间（或金属间和内部）介电层的电介质衬垫的线间可靠性增强

    公开(公告)号：US07402514B2

    公开(公告)日：2008-07-22

    申请号：US10350451

    申请日：2003-01-24

    申请人： Robert Tsu ,  Joe W. McPherson ,  William R. McKee ,  Thomas Bonifield

    发明人： Robert Tsu ,  Joe W. McPherson ,  William R. McKee ,  Thomas Bonifield

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76831 ,  H01L21/76807

    摘要： An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an opening in the first insulating layer (layer 124 or 128 of FIGS. 1-4), the opening having a top, a bottom and sidewalls and is situated between the first conductor and the second conductor; forming a second insulating layer (layer 134, 138, and 142 of FIGS. 3 and 4) exclusively on the sidewalls of the opening thereby leaving a smaller opening in the first insulating layer; forming a conductive material (material 140 of FIGS. 3 and 4) in the smaller opening; and wherein the first insulating layer is comprised of a low-k material and the second insulating layer is comprised of an insulator which has electrical leakage properties which are less than the electrical leakage properties of the first insulating layer.

    摘要翻译： 本发明的一个实施例是一种在第一导体和第二导体之间提供连接的方法，其中第一导体位于第二导体下方并由第一绝缘层分开，该方法包括以下步骤：在 第一绝缘层（图1-4的层124或128），开口具有顶部，底部和侧壁，并且位于第一导体和第二导体之间; 仅在开口的侧壁上形成第二绝缘层（图3和4的层134,138和142），从而在第一绝缘层中留下较小的开口; 在较小的开口中形成导电材料（图3和图4的材料140） 并且其中所述第一绝缘层由低k材料构成，并且所述第二绝缘层由具有小于所述第一绝缘层的漏电特性的漏电特性的绝缘体构成。

    Semiconductor integrated circuit device including a DRAM having reduced parasitic bit line capacity and method of manufacturing same
    5.
    发明授权
    Semiconductor integrated circuit device including a DRAM having reduced parasitic bit line capacity and method of manufacturing same 有权
    包括具有降低的寄生位线容量的DRAM的半导体集成电路器件及其制造方法

    公开(公告)号：US06168985A

    公开(公告)日：2001-01-02

    申请号：US09332894

    申请日：1999-06-15

    申请人： Isamu Asano ,  Robert Tsu

    发明人： Isamu Asano ,  Robert Tsu

    IPC分类号： H01L218242

    CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10897

    摘要： In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors. A position at which a transistor for selectively connecting the memory cell portion and the peripheral circuit portion is formed may be a boundary, or a position inside a boundary region between the memory cell portion and the peripheral circuit portion may be a boundary, where the thickness change is effected.

    摘要翻译： 在具有形成在半导体衬底的主表面的第一部分处的存储单元部分和形成在半导体衬底的主表面的第二部分的外围电路部分的DRAM的半导体集成电路器件中，位线导体和第一 用于连接存储单元部分和外围电路部分以便在它们之间交换信号的外围电路部分中的高级互连导体由同时形成并因此存在于同一水平的导体层构成。 导体层存在于诸如周边电路部分的存储单元部分的外部位置，并且构成外围电路部分的第一级互连导体的导体层的部分的厚度大于外围电路部分的厚度 构成位线导体的导体层。 形成用于选择性地连接存储单元部分和外围电路部分的晶体管的位置可以是边界，或者存储单元部分和外围电路部分之间的边界区域内的位置可以是边界，其中厚度 改变了。

    Method of manufacturing semiconductor integrated circuit device including a DRAM having reduced parasitic bit line capacity
    6.
    发明授权
    Method of manufacturing semiconductor integrated circuit device including a DRAM having reduced parasitic bit line capacity 失效
    包括具有降低的寄生位线容量的DRAM的半导体集成电路器件的制造方法

    公开(公告)号：US6037207A

    公开(公告)日：2000-03-14

    申请号：US968586

    申请日：1997-11-13

    申请人： Isamu Asano ,  Robert Tsu

    发明人： Isamu Asano ,  Robert Tsu

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10897

    摘要： In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors. A position at which a transistor for selectively connecting the memory cell portion and the peripheral circuit portion is formed may be a boundary, or a position inside a boundary region between the memory cell portion and the peripheral circuit portion may be a boundary, where the thickness change is effected.

    摘要翻译： 在具有形成在半导体衬底的主表面的第一部分处的存储单元部分和形成在半导体衬底的主表面的第二部分的外围电路部分的DRAM的半导体集成电路器件中，位线导体和第一 用于连接存储单元部分和外围电路部分以便在它们之间交换信号的外围电路部分中的高级互连导体由同时形成并因此存在于同一水平的导体层构成。 导体层存在于诸如周边电路部分的存储单元部分的外部位置，并且构成外围电路部分的第一级互连导体的导体层的部分的厚度大于外围电路部分的厚度 构成位线导体的导体层。 形成用于选择性地连接存储单元部分和外围电路部分的晶体管的位置可以是边界，或者存储单元部分和外围电路部分之间的边界区域内的位置可以是边界，其中厚度 改变了。

    Yield improvement of dual damascene fabrication through oxide filling
    7.
    发明授权
    Yield improvement of dual damascene fabrication through oxide filling 有权
    通过氧化物填充的双镶嵌制造的产量提高

    公开(公告)号：US06461955B1

    公开(公告)日：2002-10-08

    申请号：US09521325

    申请日：2000-03-09

    申请人： Robert Tsu ,  Qi-Zhong Hong ,  William R. Mckee

    发明人： Robert Tsu ,  Qi-Zhong Hong ,  William R. Mckee

    IPC分类号： H01L214763

    CPC分类号： H01L21/76808 ,  H01L21/76805

    摘要： A dual damascene process. After the via etch, a via protect layer (114) is deposited in the via (112). The via protect layer (114) comprises a material that has a dry etch rate at least equal to that of the IMD (108) and a wet etch rate that is approximately 100 times that of the IMD (108) or greater. Exemplary materials include PSG, BPSG, and HSQ. The trench pattern (120) is formed and both the via protect layer (114) and IMD (108) are etched. The remaining portions of the via protect layer (114) are then removed prior to forming the metal layer (122).

    摘要翻译： 双镶嵌工艺。 在通孔蚀刻之后，通孔保护层（114）沉积在通孔（112）中。 通孔保护层（114）包括具有至少等于IMD（108）的干蚀刻速率的干蚀刻速率和大约为IMD（108）或更大的100倍的湿蚀刻速率的材料。 示例性材料包括PSG，BPSG和HSQ。 形成沟槽图案（120）并蚀刻通孔保护层（114）和IMD（108）。 然后在形成金属层（122）之前去除通孔保护层（114）的剩余部分。

    Method of manufacturing a semiconductor integrated circuit device having a memory cell array and a peripheral circuit region
    9.
    发明授权
    Method of manufacturing a semiconductor integrated circuit device having a memory cell array and a peripheral circuit region 有权
    具有存储单元阵列和外围电路区域的半导体集成电路器件的制造方法

    公开(公告)号：US06696337B2

    公开(公告)日：2004-02-24

    申请号：US10166013

    申请日：2002-06-11

    申请人： Isamu Asano ,  Robert Tsu

    发明人： Isamu Asano ,  Robert Tsu

    IPC分类号： H01L218242

    CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10897

    摘要： In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors. A position at which a transistor for selectively connecting the memory cell portion and the peripheral circuit portion is formed may be a boundary, or a position inside a boundary region between the memory cell portion and the peripheral circuit portion may be a boundary, where the thickness change is effected.

    摘要翻译： 在具有形成在半导体衬底的主表面的第一部分处的存储单元部分和形成在半导体衬底的主表面的第二部分的外围电路部分的DRAM的半导体集成电路器件中，位线导体和第一 用于连接存储单元部分和外围电路部分以便在它们之间交换信号的外围电路部分中的高级互连导体由同时形成并因此存在于同一水平的导体层构成。 导体层存在于诸如周边电路部分的存储单元部分的外部位置，并且构成外围电路部分的第一级互连导体的导体层的部分的厚度大于外围电路部分的厚度 构成位线导体的导体层。 形成用于选择性地连接存储单元部分和外围电路部分的晶体管的位置可以是边界，或者存储单元部分和外围电路部分之间的边界区域内的位置可以是边界，其中厚度 改变了。

    Method of manufacturing a semiconductor integrated circuit device including a DRAM having reduced parasitic bit line capacity
    10.
    发明授权
    Method of manufacturing a semiconductor integrated circuit device including a DRAM having reduced parasitic bit line capacity 有权
    包括具有降低的寄生位线容量的DRAM的半导体集成电路器件的制造方法

    公开(公告)号：US06417045B1

    公开(公告)日：2002-07-09

    申请号：US09642586

    申请日：2000-08-22

    申请人： Isamu Asano ,  Robert Tsu

    发明人： Isamu Asano ,  Robert Tsu

    IPC分类号： H01L218242

    CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10897

    摘要： In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors. A position at which a transistor for selectively connecting the memory cell portion and the peripheral circuit portion is formed may be a boundary, or a position inside a boundary region between the memory cell portion and the peripheral circuit portion may be a boundary, where the thickness change is effected.

    摘要翻译： 在具有形成在半导体衬底的主表面的第一部分处的存储单元部分和形成在半导体衬底的主表面的第二部分的外围电路部分的DRAM的半导体集成电路器件中，位线导体和第一 用于连接存储单元部分和外围电路部分以便在它们之间交换信号的外围电路部分中的高级互连导体由同时形成并因此存在于同一水平的导体层构成。 导体层存在于诸如周边电路部分的存储单元部分的外部位置，并且构成外围电路部分的第一级互连导体的导体层的部分的厚度大于外围电路部分的厚度 构成位线导体的导体层。 形成用于选择性地连接存储单元部分和外围电路部分的晶体管的位置可以是边界，或者存储单元部分和外围电路部分之间的边界区域内的位置可以是边界，其中厚度 改变了。