公开(公告)号：US20070098012A1

公开(公告)日：2007-05-03

申请号：US11381561

申请日：2006-05-04

申请人： Christopher Pettey ,  Asif Khan ,  Annette Pagan ,  Richard Pekkala ,  Robert Utley

发明人： Christopher Pettey ,  Asif Khan ,  Annette Pagan ,  Richard Pekkala ,  Robert Utley

IPC分类号： H04L12/66

CPC分类号： H04L67/24 ,  H04L49/351 ,  H04L49/356

摘要： An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

摘要翻译： 提供了一种用于允许在每个处理复合体的加载/存储结构内的多个处理复合体之间共享和/或分区I / O设备的装置和方法，而不需要修改处理的操作系统或驱动程序软件 复合物。 该装置和方法包括用于将每个处理复合体选择性地耦合到一个或多个共享I / O设备的开关。 该装置和方法还包括将信息放置在交换机和I / O设备之间传输的分组内，以识别分组与哪个处理复合体相关联。 本发明还包括共享I / O设备内的装置和方法，以允许共享I / O设备独立地为每个处理复合体提供服务。

公开(公告)号：US20050025119A1

公开(公告)日：2005-02-03

申请号：US10827622

申请日：2004-04-19

申请人： Christopher Pettey ,  Asif Khan ,  Annette Pagan ,  Richard Pekkala ,  Robert Utley

发明人： Christopher Pettey ,  Asif Khan ,  Annette Pagan ,  Richard Pekkala ,  Robert Utley

IPC分类号： G06F13/00

CPC分类号： H04L49/25 ,  H04L49/253 ,  H04L49/254 ,  H04L49/602 ,  H04L49/604

摘要： An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality of I/O ports is configured to route transactions between said plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint, where the first shared input/output endpoint is configured to request/complete said transactions for each of the plurality of operating system domains. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the transactions between the first plurality of I/O ports and the second I/O port.

摘要翻译： 提供了一种能够在多个操作系统域之间共享I / O设备的装置和方法。 该装置具有第一多个I / O端口，第二I / O端口和核心逻辑。 第一组多个I / O端口通过加载存储架构耦合到多个操作系统域。 第一多个I / O端口中的每一个被配置为在所述多个操作系统域和交换设备之间路由事务。 所述第二I / O端口耦合到第一共享输入/输出端点，其中所述第一共享输入/输出端点被配置为请求/完成所述多个操作系统域中的每一个的所述事务。 核心逻辑耦合到第一组多个I / O端口和第二I / O端口。 核心逻辑将路由第一组多个I / O端口和第二I / O端口之间的事务。

公开(公告)号：US20050147117A1

公开(公告)日：2005-07-07

申请号：US11048393

申请日：2005-01-31

申请人： Christopher Pettey ,  Asif Khan ,  Annette Pagan ,  Richard Pekkala ,  Robert Utley

发明人： Christopher Pettey ,  Asif Khan ,  Annette Pagan ,  Richard Pekkala ,  Robert Utley

IPC分类号： H04L12/28

CPC分类号： H04L49/356

摘要： An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus includes a first plurality of I/O ports, a second I/O port, and a plurality of port initialization logic elements. The first plurality of I/O ports is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality of I/O ports routes transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. One of the plurality of port initialization logic elements is coupled to the second I/O port and remaining ones of the plurality of port initialization logic elements are each coupled to a corresponding one of the first plurality of I/O ports. The plurality of port initialization logic elements is configured to initialize corresponding links between each of the plurality of operating system domains and the switching apparatus, and between the first shared input/output endpoint and the switching apparatus, to support the transactions, where each of the plurality of port initialization logic elements automatically configures a corresponding polarity for each of the first plurality of I/O ports and the second I/O port, and where the corresponding polarity is in a default polarity prior to being configured.

摘要翻译： 提供了一种能够在多个操作系统域之间共享I / O设备的装置和方法。 该装置包括第一多个I / O端口，第二I / O端口和多个端口初始化逻辑元件。 第一组多个I / O端口通过加载存储架构耦合到多个操作系统域。 第一多个I / O端口中的每一个在多个操作系统域和交换设备之间路由事务。 第二个I / O端口耦合到第一个共享输入/输出端点。 第一共享输入/输出端点被配置为请求/完成多个操作系统域中的每一个的事务。 多个端口初始化逻辑元件中的一个耦合到第二I / O端口，并且多个端口初始化逻辑元件中的其余端口初始化逻辑元件中的每一个耦合到第一多个I / O端口中的对应的一个。 多个端口初始化逻辑元件被配置为初始化多个操作系统域和交换设备中的每一个之间以及第一共享输入/输出端点与交换设备之间的对应链路，以支持交易，其中， 多个端口初始化逻辑元件自动地配置第一多个I / O端口和第二I / O端口中的每一个的相应极性，并且其中在配置之前相应的极性处于默认极性。

公开(公告)号：US20050071528A1

公开(公告)日：2005-03-31

申请号：US10675716

申请日：2003-09-30

申请人： Robert Utley

发明人： Robert Utley

IPC分类号： G06F3/00 ,  H04L12/56

CPC分类号： H04L47/10 ,  H04L47/32 ,  H04L49/30 ,  H04L49/55

摘要： A processor includes a plurality of input ports, memory circuitry for storing data blocks associated with protocol data units (PDUs) and received by the processor at the input ports, and controller circuitry coupled to the memory circuitry. The controller circuitry is operative to discard certain ones of the data blocks received at the input ports in an oversubscription condition in which the received data blocks exceed a designated capacity of the processor. A discarded data block indicator is generated for a given one of the input ports if a data block received at the given input port for a particular PDU is discarded. One or more additional data blocks received at the given input port for the particular PDU are discarded based at least in part on the discarded data block indicator. The oversubscription condition may thereby be overcome in a manner which advantageously minimizes the number of received PDUs that are corrupted through discarded data blocks.

摘要翻译： 处理器包括多个输入端口，用于存储与协议数据单元（PDU）相关联并由处理器在输入端口接收的数据块的存储器电路，以及耦合到存储器电路的控制器电路。 控制器电路可操作以丢弃在其中所接收的数据块超过处理器的指定容量的超额预订条件下在输入端口接收的某些数据块。 如果在特定PDU的给定输入端口处接收的数据块被丢弃，则为给定的一个输入端口生成丢弃的数据块指示符。 至少部分地基于所丢弃的数据块指示符来丢弃在给定输入端口处为特定PDU接收的一个或多个附加数据块。 从而可以以有利地最小化通过丢弃的数据块损坏的接收PDU的数量的方式来克服超额预订条件。

公开(公告)号：US20070025354A1

公开(公告)日：2007-02-01

申请号：US11379264

申请日：2006-04-19

申请人： Christopher Pettey ,  Richard Pekkala ,  Asif Khan ,  Annette Pagan ,  Robert Utley

发明人： Christopher Pettey ,  Richard Pekkala ,  Asif Khan ,  Annette Pagan ,  Robert Utley

IPC分类号： H04L12/56

CPC分类号： G06F13/12

摘要： An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

公开(公告)号：US20060018342A1

公开(公告)日：2006-01-26

申请号：US11235514

申请日：2005-09-26

申请人： Christopher Pettey ,  Asif Khan ,  Annette Pagan ,  Richard Pekkala ,  Robert Utley

发明人： Christopher Pettey ,  Asif Khan ,  Annette Pagan ,  Richard Pekkala ,  Robert Utley

IPC分类号： H04J3/22

CPC分类号： H04L67/24 ,  H04L49/351 ,  H04L49/356

摘要： An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

公开(公告)号：US20050102437A1

公开(公告)日：2005-05-12

申请号：US10972669

申请日：2004-10-25

申请人： Christopher Pettey ,  Asif Khan ,  Annette Pagan ,  Richard Pekkala ,  Robert Utley

发明人： Christopher Pettey ,  Asif Khan ,  Annette Pagan ,  Richard Pekkala ,  Robert Utley

IPC分类号： G06F3/00

CPC分类号： G06F13/4022

摘要： An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and link training logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality of I/O ports is configured to route transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. The link training logic is coupled to the second I/O port. The link training logic initializes a link between the second I/O port and the first shared input/output endpoint to support the transactions corresponding to the each of the plurality of operating system domains. The link is initialized in a manner that is transparent to the plurality of operating system domains.

摘要翻译： 提供了一种能够在多个操作系统域之间共享I / O设备的装置和方法。 该装置具有第一多个I / O端口，第二I / O端口和链路训练逻辑。 第一组多个I / O端口通过加载存储架构耦合到多个操作系统域。 第一多个I / O端口中的每一个被配置为在多个操作系统域和交换设备之间路由事务。 第二个I / O端口耦合到第一个共享输入/输出端点。 第一共享输入/输出端点被配置为请求/完成多个操作系统域中的每一个的事务。 链路训练逻辑耦合到第二I / O端口。 链路训练逻辑初始化第二I / O端口和第一共享输入/输出端点之间的链路，以支持对应于多个操作系统域中的每一个的事务。 链接以对多个操作系统域透明的方式被初始化。

公开(公告)号：US20060184711A1

公开(公告)日：2006-08-17

申请号：US11278417

申请日：2006-04-01

申请人： Christopher Pettey ,  Asif Khan ,  Annette Pagan ,  Richard Pekkala ,  Robert Utley

发明人： Christopher Pettey ,  Asif Khan ,  Annette Pagan ,  Richard Pekkala ,  Robert Utley

IPC分类号： G06F13/00

CPC分类号： H04L69/18

摘要： An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains (OSDs) through a load-store fabric, each routing transactions between the plurality of OSDs and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint requests/completes the transactions for each of the plurality of OSDs. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the transactions between the first plurality of I/O ports and the second I/O port. The core logic designates a corresponding one of the plurality of OSDs according to a variant of a protocol, where the protocol provides for routing of the transactions only for a single OSD.

摘要翻译： 提供了一种能够在多个操作系统域之间共享I / O设备的装置和方法。 该装置具有第一多个I / O端口，第二I / O端口和核心逻辑。 第一组多个I / O端口通过加载存储结构耦合到多个操作系统域（OSD），每个路由在多个OSD和交换设备之间进行事务处理。 第二个I / O端口耦合到第一个共享输入/输出端点。 第一共享输入/输出端点请求/完成多个OSD中的每一个的事务。 核心逻辑耦合到第一组多个I / O端口和第二I / O端口。 核心逻辑将路由第一组多个I / O端口和第二I / O端口之间的事务。 核心逻辑根据协议的变体指定多个OSD中的对应的一个，其中该协议仅提供用于单个OSD的事务路由。

公开(公告)号：US20060018341A1

公开(公告)日：2006-01-26

申请号：US11235513

申请日：2005-09-26

申请人： Christopher Pettey ,  Asif Khan ,  Annette Pagan ,  Richard Pekkala ,  Robert Utley

发明人： Christopher Pettey ,  Asif Khan ,  Annette Pagan ,  Richard Pekkala ,  Robert Utley

IPC分类号： H04J3/22

CPC分类号： H04L67/24 ,  H04L49/351 ,  H04L49/356

摘要： An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

公开(公告)号：US20050086416A1

公开(公告)日：2005-04-21

申请号：US10675717

申请日：2003-09-30

申请人： Robert Utley

发明人： Robert Utley

IPC分类号： G06F12/00

CPC分类号： H04L49/901 ,  H04L49/90 ,  H04L49/9073

摘要： A processor includes controller circuitry operative to control the storage of a plurality of separate linked list data structures for protocol data units received by the processor. The linked list data structures are stored in memory circuitry associated with the processor, and the memory circuitry is arranged in a plurality of banks. The plurality of banks are configured to store respective ones of the plurality of separate linked list data structures, such that each of the plurality of banks stores a corresponding one of the plurality of separate linked list data structures. The linked list data structures are accessed in an alternating manner that reduces the likelihood of access conflicts between the banks. The processor may be configured as a network processor integrated circuit to provide an interface between a network and a switch fabric in a router or switch.

摘要翻译： 处理器包括控制器电路，其操作用于控制由处理器接收的协议数据单元的多个单独的链表列表数据结构的存储。 链表数据结构存储在与处理器相关联的存储器电路中，并且存储器电路被布置在多个存储体中。 多个存储体被配置为存储多个单独的链表数据结构中的相应数据结构，使得多个存储体中的每个存储多个分离的链表数据结构中的相应一个。 以交替的方式访问链表数据结构，从而降低了存储体之间访问冲突的可能性。 处理器可以被配置为网络处理器集成电路，以在路由器或交换机中的网络和交换机结构之间提供接口。