-
公开(公告)号：US4878209A
公开(公告)日：1989-10-31
申请号：US169544
申请日：1988-03-17
申请人： Robert W. Bassett , William R. Griffin , Susan A. Murphy , John G. Petrovick, Jr. , James R. Varner , Dennis R. Whittaker
发明人： Robert W. Bassett , William R. Griffin , Susan A. Murphy , John G. Petrovick, Jr. , James R. Varner , Dennis R. Whittaker
IPC分类号： G01R31/26 , G01R31/28 , G01R31/30 , G01R31/317 , G11C29/50
CPC分类号： G11C29/028 , G01R31/3016 , G11C29/50 , G11C29/50012 , G11C17/14
摘要： An apparatus and method for testing an access time of a macro embedded in a LSI chip. The apparatus includes a logical gate connected to the output latches of the macro, thereby controlling the access time of the macro, and a test latch for determining an on-chip delay time between a test signal for enabling the output latches and an input signal for enabling the macro. The method includes the steps of determining the on-chip delay time between the test signal and the input signal, thereby allowing the test signal to be synchronized with the input signal, supplying the synchronized test signal to the output latches for a manufacturer specified macro access time, and testing the latched output data from the macro.
-
2.发明授权Read/write memory device with an embedded read-only pattern and method for providing same 失效具有嵌入式只读模式的读/写存储器件及其提供方法
公开(公告)号：US4841485A
公开(公告)日：1989-06-20
申请号：US116818
申请日：1987-11-05
申请人： Ronald J. Prilik , James R. Varner
发明人： Ronald J. Prilik , James R. Varner
摘要： A memory array device with an embedded self-test binary pattern. The device has an array of bistable cells formed with first and second sides that are oppositely connected to a first voltage line or a second voltage line. If the first and second voltage lines are energized at the same voltage level, each of the bistable cells will function in a normal bistable mode. If the first and second voltage lines are energized at different levels, each of the bistable cells will function in an embedded binary pattern mode.
-
搜索结果
2 条记录 (耗时 0.044 秒)
