公开(公告)号：US4889405A

公开(公告)日：1989-12-26

申请号：US250903

申请日：1988-09-29

申请人： Robert Walker ,  Robert Fitzgerald ,  Hans-Dieter Bippus

发明人： Robert Walker ,  Robert Fitzgerald ,  Hans-Dieter Bippus

IPC分类号： G02B6/24 ,  G02B6/38

CPC分类号： G02B6/3841 ,  G02B6/3803 ,  G02B6/3805 ,  G02B6/3806 ,  G02B6/3838

摘要： Optical wave guides are interconnected with the use of two interfitting shell parts which when fitted together form a continuous tubular channel for receiving the wave guides between there. For this purpose a carrier shell part is provided with a continuous longitudinal groove of a size to accommodate a cover shell part and each part has a longitudinally extending receiving channel portion of complementary form which fit together and form a continuous receiving channel for the optical wave guides which are to be interconnected. After the wave guides are placed end to end in the longitudinally extending wave guide receiving channels defined in the carrier shell, a cover shell is engaged over the carrier shell in a manner which positions it complementary optical wave guide channel with the wave guide channel defined on the carrier shell portion. Wave guide channels are advantageously made with curved up portions at respective ends of the interfitting carrier shell and cover shell. Advantageously, the cover shell has terminal rib portions which engage over weak edges of the outer surface of the wave guide carrier shell.

摘要翻译： 光波导通过使用两个相互配合的外壳部件相互连接，当它们装配在一起时形成连续的管状通道，用于接收波导之间的波导。 为此目的，承载壳部分设置有尺寸适于盖壳部分的连续纵向凹槽，并且每个部分具有互补形式的纵向延伸的接收通道部分，其配合在一起并形成用于光波导的连续的接收通道 哪些是互连的。 在波导被端对端设置在限定在载体壳体中的纵向延伸的波导管接收通道中之后，盖壳体以使其互补的光波导通道定位的方式与载体外壳接合，波导通道限定在 载体壳部分。 波导通道有利地在对接载体壳和盖壳的相应端部处具有弯曲的部分。 有利地，盖壳具有接合在波导载体外壳的外表面的弱边缘上的端子肋部分。

公开(公告)号：USD693753S1

公开(公告)日：2013-11-19

申请号：US29446915

申请日：2013-02-28

申请人： Winnie Cheung ,  Stephen J. Sowinski ,  Clifford Wilkins ,  Robert Walker ,  Klaus Busse

设计人： Winnie Cheung ,  Stephen J. Sowinski ,  Clifford Wilkins ,  Robert Walker ,  Klaus Busse

公开(公告)号：US08527927B2

公开(公告)日：2013-09-03

申请号：US12697058

申请日：2010-01-29

申请人： Robert Walker ,  Mahesh A. Iyer

发明人： Robert Walker ,  Mahesh A. Iyer

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： Some embodiments provide a system that facilitates the creation of a design in an electronic design automation (EDA) application. During operation, the system determines a processing order for processing a set of cells in the design. In some embodiments, the processing order can be a reverse-levelized processing order. Next, the system may select a cell for performing area recovery according to the processing order. The system may then tentatively perform an area-recovery operation on the selected cell. Next, the system may determine a zone around the selected cell. Next, the system may propagate arrival times within the zone to obtain updated slack values at endpoints of the zone. The system may compute one or more timing metrics at the endpoints. If the updated slack values do not degrade the timing metric(s) at the endpoints, the system may accept the area-recovery operation of the selected cell.

摘要翻译： 一些实施例提供了一种便于在电子设计自动化（EDA）应用中创建设计的系统。 在操作期间，系统确定用于处理设计中的一组单元的处理顺序。 在一些实施例中，处理顺序可以是反向级别化的处理顺序。 接下来，系统可以根据处理顺序选择用于执行区域恢复的单元。 然后，系统可以暂时对所选择的小区执行区域恢复操作。 接下来，系统可以确定所选择的单元周围的区域。 接下来，系统可以在区域内传播到达时间，以在该区域的端点处获得更新的松弛值。 系统可以计算端点处的一个或多个时序度量。 如果更新的松弛值不降低端点处的定时度量，则系统可以接受所选小区的区域恢复操作。

公开(公告)号：US08266570B2

公开(公告)日：2012-09-11

申请号：US12697077

申请日：2010-01-29

申请人： Robert Walker ,  Mahesh A. Iyer

发明人： Robert Walker ,  Mahesh A. Iyer

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： Some embodiments provide techniques and systems for improving the efficiency of area recovery in an electronic design automation (EDA) flow. During operation, the system determines a utilization of a region from a set of regions in a design floorplan. Next, the system performs area recovery (e.g., by using a processor) on the region based at least on the utilization. Specifically, the system can overlay the design floorplan with a grid, wherein the grid comprises a set of grid cells and uses the grid cells as the set of regions. The grid can be associated with a predetermined number of rows and a predetermined number of columns. The system can determine the utilization of the region by calculating the utilization as a cell area of the region divided by a placement area of the region. The utilization can be incrementally calculated during the creation and optimization of the design.

摘要翻译： 一些实施例提供用于提高电子设计自动化（EDA）流程中的区域恢复效率的技术和系统。 在操作期间，系统确定在设计平面图中来自一组区域的区域的利用率。 接下来，系统至少基于利用率在该区域上执行区域恢复（例如，通过使用处理器）。 具体来说，该系统可以将设计平面图与网格重叠，其中网格包括一组网格单元并且使用网格单元作为一组区域。 网格可以与预定数量的行和预定数量的列相关联。 该系统可以通过计算作为该区域的单元格区域除以该区域的放置区域的利用率来确定该区域的利用率。 可以在设计的创建和优化期间逐步计算利用率。

公开(公告)号：US08250312B2

公开(公告)日：2012-08-21

申请号：US12432610

申请日：2009-04-29

申请人： Robert Walker ,  Dan Skinner

发明人： Robert Walker ,  Dan Skinner

IPC分类号： G06F13/20

CPC分类号： G06F12/0646 ,  G06F13/1668 ,  G06F2212/1041 ,  G11C7/1075

摘要： Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks.

摘要翻译： 多端口存储设备的实施例可以包括多个端口和多个存储器组，其中一些存储器组中的一些是每个端口的本地的，并且其中一些对于每个端口是非本地的。 存储器设备可以包括配置寄存器，其存储指示存储器组到端口的映射的配置数据。 响应于配置数据，例如，转向逻辑可以将每个端口耦合到一个或所有本地存储器组，或者耦合到一个或所有非本地存储体。

公开(公告)号：US20110191740A1

公开(公告)日：2011-08-04

申请号：US12697168

申请日：2010-01-29

申请人： Robert Walker ,  Mahesh A. Iyer ,  Amir H. Mottaez

发明人： Robert Walker ,  Mahesh A. Iyer ,  Amir H. Mottaez

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F17/5081

摘要： Some embodiments of the present invention provide techniques and systems for efficiently optimizing a circuit design for one or more multi-mode multi-corner (MCMM) scenarios. A system can select an optimizing transformation for a logic gate, which if applied to the logic gate, does not degrade a timing metric in a local context of the logic gate. Next, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in a zone around the logic gate. If so, the system can reject the optimizing transformation. Otherwise, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in the circuit design. If so, the system can reject the optimizing transformation. Otherwise, the system can accept the optimizing transformation.

摘要翻译： 本发明的一些实施例提供用于有效地优化一个或多个多模式多角（MCMM）场景的电路设计的技术和系统。 系统可以选择用于逻辑门的优化变换，其如果应用于逻辑门，则不降低逻辑门的本地上下文中的定时度量。 接下来，系统可以确定将优化变换应用于逻辑门是否会降低逻辑门周围区域中的定时度量。 如果是这样，系统可以拒绝优化转换。 否则，系统可以确定将优化变换应用于逻辑门是否会降低电路设计中的定时度量。 如果是这样，系统可以拒绝优化转换。 否则，系统可以接受优化转换。

公开(公告)号：US20110191738A1

公开(公告)日：2011-08-04

申请号：US12697077

申请日：2010-01-29

申请人： Robert Walker ,  Mahesh A. Iyer

发明人： Robert Walker ,  Mahesh A. Iyer

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： Some embodiments provide techniques and systems for improving the efficiency of area recovery in an electronic design automation (EDA) flow. During operation, the system determines a utilization of a region from a set of regions in a design floorplan. Next, the system performs area recovery (e.g., by using a processor) on the region based at least on the utilization. Specifically, the system can overlay the design floorplan with a grid, wherein the grid comprises a set of grid cells and uses the grid cells as the set of regions. The grid can be associated with a predetermined number of rows and a predetermined number of columns. The system can determine the utilization of the region by calculating the utilization as a cell area of the region divided by a placement area of the region. The utilization can be incrementally calculated during the creation and optimization of the design.

摘要翻译： 一些实施例提供用于提高电子设计自动化（EDA）流程中的区域恢复效率的技术和系统。 在操作期间，系统确定在设计平面图中来自一组区域的区域的利用率。 接下来，系统至少基于利用率在该区域上执行区域恢复（例如，通过使用处理器）。 具体来说，该系统可以将设计平面图与网格重叠，其中网格包括一组网格单元并且使用网格单元作为一组区域。 网格可以与预定数量的行和预定数量的列相关联。 该系统可以通过计算作为该区域的单元格区域除以该区域的放置区域的利用率来确定该区域的利用率。 可以在设计的创建和优化期间逐步计算利用率。

公开(公告)号：US20070245283A1

公开(公告)日：2007-10-18

申请号：US11279758

申请日：2006-04-14

申请人： Robert Allen ,  Michael Gray ,  Fuok-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Robert Walker

发明人： Robert Allen ,  Michael Gray ,  Fuok-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Robert Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method comprises extracting a hierarchical grid constraint set and modeling one or more critical objects of at least one cell as a variable set. The method further comprises solving a linear programming problem based on the hierarchical grid constraint set with the variable set to provide initial locations of the critical objects of the at least one cell and determining target on-grid locations of the one or more critical objects in the at least one cell using the results of the linear programming solution.

摘要翻译： 一种方法包括提取分级网格约束集合并将至少一个小区的一个或多个关键对象建模为变量集。 该方法还包括基于具有变量集合的分级网格约束集来解决线性规划问题，以提供至少一个小区的关键对象的初始位置并且确定所述至少一个小区中的一个或多个关键对象的目标并网位置 使用线性规划解决方案的结果的至少一个小区。

公开(公告)号：US20070110367A1

公开(公告)日：2007-05-17

申请号：US11272871

申请日：2005-11-15

申请人： Robert Walker ,  Stephen Mihailov ,  Ping Lu ,  Dan Grobnic ,  Xiaoli Dai ,  Huimin Ding ,  George Henderson ,  Christopher Smelser

发明人： Robert Walker ,  Stephen Mihailov ,  Ping Lu ,  Dan Grobnic ,  Xiaoli Dai ,  Huimin Ding ,  George Henderson ,  Christopher Smelser

IPC分类号： G02B6/34 ,  G02B6/42

CPC分类号： G01J1/04 ,  G01J1/0204 ,  G01J1/0407 ,  G01J1/0477 ,  G01J1/4228 ,  G01J9/00 ,  G02B6/02085 ,  G02B6/29323 ,  G02B6/29385 ,  G02B6/4215

摘要： The invention relates to an optical waveguide device for monitoring a characteristics of light, e.g. a wavelength. The device incorporates a waveguide, such as an optical fiber, with an embedded tilted Bragg grating operating in a regime of wavelength detuning. The grating is designed to disperse light azimuthally in two or more different directions about the fiber axis, said directions changing with wavelength. A photodetector array is provided for detecting the azimuthal distribution of light. A processor coupled to the photodetector array determines wavelength information from the detected azimuthal distribution of the out-coupled light.

摘要翻译： 本发明涉及一种用于监测光的特性的光波导器件，例如， 一个波长。 该器件包括诸如光纤的波导，其具有以波长失谐的状态工作的嵌入式倾斜布拉格光栅。 光栅被设计成围绕光纤轴在两个或更多个不同方向上以方位角分散光，所述方向随着波长而变化。 提供了用于检测光的方位角分布的光电检测器阵列。 耦合到光电检测器阵列的处理器根据检测出的外耦合光的方位分布来确定波长信息。

公开(公告)号：US07145483B2

公开(公告)日：2006-12-05

申请号：US10730443

申请日：2003-12-08

申请人： Robert Walker

发明人： Robert Walker

IPC分类号： H03M5/02

CPC分类号： H04L25/028 ,  H03M5/04 ,  H04L25/4917

摘要： A chip to chip interface comprises a driver configured to receive a data signal and provide an output signal at a first level in response to receiving an odd number of consecutive logic highs in the data signal, at a second level in response to receiving an odd number of consecutive logic lows in the data signal, at a third level in response to receiving an even number of consecutive logic highs in the data signal and at a fourth level in response to receiving an even number of consecutive logic lows in the data signal.

摘要翻译： 芯片到芯片接口包括驱动器，其被配置为接收数据信号并响应于在第二电平响应于接收奇数而在第二电平上接收奇数个数据信号中的连续逻辑高电平而提供第一电平的输出信号 响应于在数据信号中接收到偶数个连续的逻辑高电平并且响应于在数据信号中接收到偶数个连续的逻辑低电平而在第四电平处在数据信号中的连续逻辑低电平。