METHOD FOR MOBILE TERMINAL TO ACCESS WIRELESS ACCESS POINT AND WIRELESS ACCESS POINT
    2.
    发明申请
    METHOD FOR MOBILE TERMINAL TO ACCESS WIRELESS ACCESS POINT AND WIRELESS ACCESS POINT 有权
    移动终端访问无线接入点和无线接入点的方法

    公开(公告)号:US20150109912A1

    公开(公告)日:2015-04-23

    申请号:US14398560

    申请日:2012-06-25

    IPC分类号: H04W28/02 H04W28/08

    摘要: A method for a mobile terminal accessing wireless access points and a wireless access point are disclosed. The method includes: after acquiring an access request of a mobile station, when determining that its load exceeds a preset first load upper limit, according to acquired connection information of other wireless access points, a first wireless access point sends a load balance request to all the other wireless access points; a wireless access point receiving the request sends a load balance feedback message to the first wireless access point, carrying its load and connection authentication information required; the first wireless access point selects a load balance feedback message carrying a minimum load from all received messages, and then sends the connection authentication information carried in the selected message to the mobile station; and the mobile station initiates an access flow to a corresponding wireless access point according to the received information.

    摘要翻译: 公开了一种移动终端访问无线接入点和无线接入点的方法。 该方法包括:在获取移动台的接入请求后,当确定其负载超过预设的第一负载上限时,根据所获取的其他无线接入点的连接信息,第一无线接入点向所有者发送负载均衡请求 其他无线接入点; 接收请求的无线接入点向第一无线接入点发送负载平衡反馈消息,承载其所需的负载和连接认证信息; 第一无线接入点从所有接收到的消息中选择承载最小负载的负载均衡反馈消息,然后将所选消息中携带的连接认证信息发送给移动台; 并且移动台根据接收到的信息发起到对应的无线接入点的接入流。

    Method for mobile terminal to access wireless access point and wireless access point
    3.
    发明授权
    Method for mobile terminal to access wireless access point and wireless access point 有权
    移动终端接入无线接入点和无线接入点的方法

    公开(公告)号:US09338689B2

    公开(公告)日:2016-05-10

    申请号:US14398560

    申请日:2012-06-25

    摘要: A method for a mobile terminal accessing wireless access points and a wireless access point are disclosed. The method includes: after acquiring an access request of a mobile station, when determining that its load exceeds a preset first load upper limit, according to acquired connection information of other wireless access points, a first wireless access point sends a load balance request to all the other wireless access points; a wireless access point receiving the request sends a load balance feedback message to the first wireless access point, carrying its load and connection authentication information required; the first wireless access point selects a load balance feedback message carrying a minimum load from all received messages, and then sends the connection authentication information carried in the selected message to the mobile station; and the mobile station initiates an access flow to a corresponding wireless access point according to the received information.

    摘要翻译: 公开了一种移动终端访问无线接入点和无线接入点的方法。 该方法包括:在获取移动台的接入请求后,当确定其负载超过预设的第一负载上限时,根据所获取的其他无线接入点的连接信息,第一无线接入点向所有者发送负载均衡请求 其他无线接入点; 接收请求的无线接入点向第一无线接入点发送负载平衡反馈消息,承载其所需的负载和连接认证信息; 第一无线接入点从所有接收到的消息中选择承载最小负载的负载均衡反馈消息,然后将所选消息中携带的连接认证信息发送给移动台; 并且移动台根据接收到的信息发起到对应的无线接入点的接入流。

    Integrated circuit designs for high speed signal processing
    4.
    发明授权
    Integrated circuit designs for high speed signal processing 失效
    用于高速信号处理的集成电路设计

    公开(公告)号:US06559693B2

    公开(公告)日:2003-05-06

    申请号:US10137988

    申请日:2002-05-02

    IPC分类号: H03K2100

    摘要: Techniques designing an electronic circuit system including multiple transistors and passive components are presented. According to one aspect of the techniques, some or all of the transistors and passive components are systematically adjusted to minimize artifacts resulting from system-level interactions among these functional building blocks. The adjustment is based on a ratio of Electrically Equivalent Channel Geometry (EECG) of each of the adjusted the transistors and passive components.

    摘要翻译: 提出了设计包括多个晶体管和无源元件的电子电路系统的技术。 根据技术的一个方面,系统地调整了一些或全部晶体管和无源组件,以最小化由这些功能构建块之间的系统级交互导致的伪影。 调整基于每个调整后的晶体管和无源元件的电子等效通道几何(EECG)的比率。

    Method of system circuit design and circuitry for high speed data communication
    5.
    发明授权
    Method of system circuit design and circuitry for high speed data communication 失效
    系统电路设计方法及高速数据通信电路

    公开(公告)号:US06433595B1

    公开(公告)日:2002-08-13

    申请号:US09947643

    申请日:2001-09-05

    IPC分类号: H03K2100

    摘要: A method of designing a system of electronic circuit is presented. With this method the circuit parameters of the components of the individual functional building blocks of the system are systematically adjusted to minimize the deteriorating effect resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a CMOS IC that is a Divide-by-16 divider where the functional building blocks are four Dividing by-2 dividers. The resulting improvement of output signal ripple from each devided stage is graphically presented. In another embodyment, the method is applied to another CMOS IC that is a Bang Bang Phase Detector where the functional building blocks are three Master Slave D-Type Flip Flops. The resulting improvement of output signal ripple is also graphically presented.

    摘要翻译: 提出了一种设计电子电路系统的方法。 使用这种方法,系统地调整系统的各个功能构建块的组件的电路参数,以最小化由这些功能构建块之间的系统级交互引起的恶化效果。 在一个实施例中,该方法被应用于作为16分频器的CMOS IC,其中功能构建块是四个除以2的分频器。 从图中可以看出,每个偏移阶段输出信号纹波的改善。 在另一个实施方式中,该方法被应用于另一个CMOS IC,它是Bang Bang相位检测器,其中功能构建块是三个主从D型触发器。 输出信号纹波的改善也以图形方式呈现。

    2-level series-gated current mode logic with inductive components for high-speed circuits
    6.
    发明授权
    2-level series-gated current mode logic with inductive components for high-speed circuits 失效
    2级串联电流模式逻辑,具有高速电路的电感元件

    公开(公告)号:US06777988B2

    公开(公告)日:2004-08-17

    申请号:US10136165

    申请日:2002-04-30

    IPC分类号: H03K2100

    CPC分类号: H03K3/356139 H03K3/012

    摘要: A fundamental building block of 2-level series-gated CML-based CMOS circuit which includes a number of inductive components for an electronic circuit system is disclosed that is capable of driving a significant level of external capacitive load at a high input clock frequency while providing a high level of output signal fidelity for optical data communication. The inductive components can be implemented as either separate inductors or as differentially coupled pairs forming a corresponding transformer element. The value of any particular inductive component is first selected to approximately resonate, at the desired output signal frequency, with its associated equivalent node capacitance but further adjusted to a final value that results in a minimum output waveform distortion for the particular application. Two exemplary cases of application, a Divide-by-2 counter and a Master Slave D-type Flip Flop are presented with associated time domain output waveforms.

    摘要翻译: 公开了一种基于2级串联门控CML的CMOS电路的基本构造块,其包括用于电子电路系统的多个电感元件,其能够以高输入时钟频率驱动显着水平的外部电容性负载,同时提供 用于光数据通信的高水平输出信号保真度。 电感元件可以实现为单独的电感器或形成形成对应的变压器元件的差分耦合对。 首先选择任何特定电感分量的值以期望的输出信号频率与其相关联的等效节点电容近似共振,但是进一步被调整到导致特定应用的最小输出波形失真的最终值。 呈现了两个示例性应用案例,一个二分之一计数器和一个主从D型触发器,具有相关的时域输出波形。