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    PORT SCANNING METHOD AND DEVICE, PORT SCANNING DETECTION METHOD AND DEVICE, PORT SCANNING SYSTEM, COMPUTER PROGRAM AND COMPUTER PROGRAM PRODUCT
    1.
    发明申请
    PORT SCANNING METHOD AND DEVICE, PORT SCANNING DETECTION METHOD AND DEVICE, PORT SCANNING SYSTEM, COMPUTER PROGRAM AND COMPUTER PROGRAM PRODUCT 有权
    端口扫描方法和设备，端口扫描检测方法和设备，端口扫描系统，计算机程序和计算机程序产品

    公开(公告)号：US20070044155A1

    公开(公告)日：2007-02-22

    申请号：US11465112

    申请日：2006-08-16

    申请人： Roman Pletka ,  Marcel Waldvogel

    发明人： Roman Pletka ,  Marcel Waldvogel

    IPC分类号： G06F11/00

    CPC分类号： H04L63/08 ,  H04L63/1458

    摘要： For port scanning an authentication bit sequence is created as an output of an authentication transformation, the authentication transformation having as input at least a given destination address and a given secret key. The authentication bit sequence is embedded in at least one authentication port scan event packet comprising the given destination address. At least one authentication port scan event packet is broadcast. Then, further port scan event packets are broadcast with given port identifiers and the given destination address. For port scanning detection, a received authentication bit sequence is derived from a least one authentication port scan event packet with identical source and destination addresses. Further port scan event packets are accepted with given port identifiers and the given destination address if authentication is given.

    摘要翻译： 对于端口扫描，创建认证比特序列作为认证转换的输出，认证转换具有至少给定目的地地址和给定秘密密钥的输入。 验证比特序列被嵌入到包括给定目的地地址的至少一个认证端口扫描事件分组中。 至少一个认证端口扫描事件包被广播。 然后，使用给定的端口标识符和给定的目的地址广播进一步的端口扫描事件分组。 对于端口扫描检测，从具有相同源和目的地址的至少一个认证端口扫描事件分组导出接收到的认证位序列。 使用给定的端口标识符接收进一步的端口扫描事件数据包，如果给出了认证，则接收给定的目标地址。

    Searching a range in a set of values in a network with distributed storage entities
    2.
    发明申请
    Searching a range in a set of values in a network with distributed storage entities 有权
    在具有分布式存储实体的网络中搜索一组值中的范围

    公开(公告)号：US20050203901A1

    公开(公告)日：2005-09-15

    申请号：US11079554

    申请日：2005-03-14

    申请人： Marcel Waldvogel ,  Roman Pletka

    发明人： Marcel Waldvogel ,  Roman Pletka

    IPC分类号： G06F7/00

    CPC分类号： G06F17/30545 ,  G06F17/30575 ,  H04L67/1097

    摘要： Methods for searching a range in a set of values in a network with distributed storage nodes. An example of a method for searching a range in a set of values in a network with distributed storage nodes according to the invention comprises the following steps. First, the range is divided up into a set of subranges by means of a hierarchical structure. Then, a query packet is generated for said set of subranges and transmitted to the distributed storage nodes for performing the query.

    摘要翻译： 用于在具有分布式存储节点的网络中搜索一组值中的范围的方法。 根据本发明的用于搜索具有分布式存储节点的网络中的一组值中的范围的方法的示例包括以下步骤。 首先，通过层次结构将范围分为一组子范围。 然后，为所述一组子范围生成查询分组，并发送到分布式存储节点以执行查询。

    LOGICAL TO PHYSICAL ADDRESS MAPPING IN STORAGE SYSTEMS COMPRISING SOLID STATE MEMORY DEVICES
    3.
    发明申请
    LOGICAL TO PHYSICAL ADDRESS MAPPING IN STORAGE SYSTEMS COMPRISING SOLID STATE MEMORY DEVICES 有权
    在包含固态存储器件的存储系统中逻辑地址映射

    公开(公告)号：US20130124794A1

    公开(公告)日：2013-05-16

    申请号：US13812377

    申请日：2011-07-25

    申请人： Werner Bux ,  Robert Haas ,  Xiao-Yu Hu ,  Roman Pletka

    发明人： Werner Bux ,  Robert Haas ,  Xiao-Yu Hu ,  Roman Pletka

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F12/0848 ,  G06F12/0866 ,  G06F2212/214 ,  G06F2212/221 ,  G06F2212/222 ,  G06F2212/466 ,  G06F2212/7201

    摘要： The present idea provides a high read and write performance from/to a solid state memory device. The main memory of the controller is not blocked by a complete address mapping table covering the entire memory device. Instead such table is stored in the memory device itself, and only selected portions of address mapping information are buffered in the main memory in a read cache and a write cache. A separation of the read cache from the write cache enables an address mapping entry being evictable from the read cache without the need to update the related flash memory page storing such entry in the flash memory device. By this design, the read cache may advantageously be stored on a DRAM even without power down protection, while the write cache may preferably be implemented in nonvolatile or other fail-safe memory. This leads to a reduction of the overall provisioning of nonvolatile or fail-safe memory and to an improved scalability and performance.

    摘要翻译： 本想法提供了从/到固态存储器件的高读/写性能。 控制器的主存储器不被覆盖整个存储器件的完整地址映射表阻止。 相反，这样的表被存储在存储器设备本身中，并且只有地址映射信息的选定部分被缓存在读取高速缓存和写入高速缓存中的主存储器中。 读取高速缓存与写入高速缓存的分离使得能够从读取的高速缓存中取出地址映射条目，而不需要在闪存设备中更新存储这样的条目的相关闪存页面。 通过这种设计，读取高速缓存可以有利地存储在DRAM上，即使没有掉电保护，而写入高速缓存也可以优选地被实现在非易失性或其它故障安全存储器中。 这导致了非易失性或故障安全存储器的总体配置的减少以及改进的可扩展性和性能。

    WRITE CACHE STRUCTURE IN A STORAGE SYSTEM
    5.
    发明申请
    WRITE CACHE STRUCTURE IN A STORAGE SYSTEM 有权
    存储系统中的写入缓存结构

    公开(公告)号：US20120131265A1

    公开(公告)日：2012-05-24

    申请号：US13283967

    申请日：2011-10-28

    申请人： Ioannis Koltsidas ,  Roman Pletka

    发明人： Ioannis Koltsidas ,  Roman Pletka

    IPC分类号： G06F12/02 ,  G06F12/08

    CPC分类号： G06F12/0868 ,  G06F12/0897 ,  G06F2212/225 ,  G06F2212/262 ,  Y02D10/13

    摘要： A method of writing data units to a storage device. The data units are cached in a first level cache sorted by logical address. A group (Gj) of sorted data units is transferred from the first level cache to a second level cache embodied in a solid state memory device. Data units of multiple groups (Gj) are sorted in the second level cache by logical address. The sorted data units stemming from the multiple groups are written to the storage device.

    摘要翻译： 将数据单元写入存储装置的方法。 数据单元被缓存在按逻辑地址排序的第一级缓存中。 排序数据单元的组（Gj）从第一级高速缓存传送到实体在固态存储器件中的第二级缓存。 多组数据单元（Gj）通过逻辑地址在第二级高速缓存中排序。 来自多个组的分类数据单元被写入存储设备。

    Method, device and computer program product for decoding a codeword
    6.
    发明授权
    Method, device and computer program product for decoding a codeword 有权
    用于解码码字的方法，设备和计算机程序产品

    公开(公告)号：US08996958B2

    公开(公告)日：2015-03-31

    申请号：US13574368

    申请日：2011-01-27

    申请人： Roy D. Cideciyan ,  Ilias Iliadis ,  Roman Pletka

    发明人： Roy D. Cideciyan ,  Ilias Iliadis ,  Roman Pletka

    IPC分类号： G11C29/00 ,  G06F11/10

    CPC分类号： G06F11/1072

    摘要： A method and apparatus for decoding a codeword received from a flash memory. The flash memory comprises multi-level flash memory cells, wherein each multi-level flash memory cell stores one symbol of the codeword. An ECC decoder is arranged for decoding the codeword into a decoded codeword and correcting a maximum number of errors. The method determines the number of errors in the codeword. If the number of errors is more than the maximum number of errors that the ECC decoder can correct, the method generates modified codewords, calculates a corrective effect of a modified codeword, and determines a decoded codeword based on the corrective effect.

    摘要翻译： 一种用于对从闪速存储器接收的码字进行解码的方法和装置。 闪速存储器包括多级闪存单元，其中每个多级闪存单元存储码字的一个符号。 ECC解码器被布置为用于将码字解码为解码码字并校正最大数量的错误。 该方法确定码字中的错误数。 如果错误数量大于ECC解码器可以纠正的最大错误数量，则该方法生成修改后的码字，计算修正码字的校正效果，并根据校正效果确定解码码字。

    Write cache structure in a storage system
    7.
    发明授权
    Write cache structure in a storage system 有权
    在存储系统中写入缓存结构

    公开(公告)号：US08990502B2

    公开(公告)日：2015-03-24

    申请号：US13283967

    申请日：2011-10-28

    申请人： Ioannis Koltsidas ,  Roman Pletka

    发明人： Ioannis Koltsidas ,  Roman Pletka

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/0868 ,  G06F12/0897 ,  G06F2212/225 ,  G06F2212/262 ,  Y02D10/13

    摘要： A method of writing data units to a storage device. The data units are cached in a first level cache sorted by logical address. A group (Gj) of sorted data units is transferred from the first level cache to a second level cache embodied in a solid state memory device. Data units of multiple groups (Gj) are sorted in the second level cache by logical address. The sorted data units stemming from the multiple groups are written to the storage device.

    摘要翻译： 将数据单元写入存储装置的方法。 数据单元被缓存在按逻辑地址排序的第一级缓存中。 排序数据单元的组（Gj）从第一级高速缓存传送到实体在固态存储器件中的第二级缓存。 多组数据单元（Gj）通过逻辑地址在第二级高速缓存中排序。 来自多个组的分类数据单元被写入存储设备。

    INTRA-BLOCK MEMORY WEAR LEVELING
    8.
    发明申请
    INTRA-BLOCK MEMORY WEAR LEVELING 失效
    内存记忆磨损

    公开(公告)号：US20110138103A1

    公开(公告)日：2011-06-09

    申请号：US12630991

    申请日：2009-12-04

    申请人： IIias IIiadis ,  Theodoros A. Antonakopoulos ,  Roman Pletka ,  Xiao-Yu Hu ,  Roy D. Cideciyan

    发明人： IIias IIiadis ,  Theodoros A. Antonakopoulos ,  Roman Pletka ,  Xiao-Yu Hu ,  Roy D. Cideciyan

    IPC分类号： G06F12/00 ,  G06F12/02

    CPC分类号： G06F12/0246 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F2212/7211

    摘要： A method for intra-block wear leveling within solid-state memory subjected to wear, having a plurality of memory cells includes the step of writing to at least certain ones of the plurality of memory cells, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level. For example, if a behavior of at least some of the plurality of memory cells is not characterized, then the method may comprise characterizing a behavior of at least some of the plurality of memory cells and writing to at least certain ones of the plurality of memory cells, based on the characterized behavior, and in a non-uniform manner.

    摘要翻译： 在具有多个存储单元的固态存储器内部进行具有多个存储单元的固态存储器内的块内损耗均衡的方法包括以非均匀方式写入多个存储单元中的至少某些存储单元的步骤， 在块内级别平衡固态存储器内的多个存储单元中的至少某些存储器单元的磨损。 例如，如果多个存储器单元中的至少一些存储器单元的行为没有被表征，则该方法可以包括表征多个存储器单元中的至少一些的行为，并写入多个存储器中的至少某些存储器 基于表征的行为，并且以不均匀的方式。

    METHOD, DEVICE AND COMPUTER PROGRAM PRODUCT FOR DECODING A CODEWORD
    10.
    发明申请
    METHOD, DEVICE AND COMPUTER PROGRAM PRODUCT FOR DECODING A CODEWORD 有权
    方法，用于解码编码器的设备和计算机程序产品

    公开(公告)号：US20120290899A1

    公开(公告)日：2012-11-15

    申请号：US13574368

    申请日：2011-01-27

    申请人： Roy D. Cideciyan ,  Ilias Iliadis ,  Roman Pletka

    发明人： Roy D. Cideciyan ,  Ilias Iliadis ,  Roman Pletka

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G06F11/1072

    摘要： A method and apparatus for decoding a codeword received from a flash memory. The flash memory comprises multi-level flash memory cells, wherein each multi-level flash memory cell stores one symbol of the codeword. An ECC decoder is arranged for decoding the codeword into a decoded codeword and correcting a maximum number of errors. The method determines the number of errors in the codeword. If the number of errors is more than the maximum number of errors that the ECC decoder can correct, the method generates modified codewords, calculates a corrective effect of a modified codeword, and determines a decoded codeword based on the corrective effect.

    摘要翻译： 一种用于对从闪速存储器接收的码字进行解码的方法和装置。 闪速存储器包括多级闪存单元，其中每个多级闪存单元存储码字的一个符号。 ECC解码器被布置为用于将码字解码为解码码字并校正最大数量的错误。 该方法确定码字中的错误数。 如果错误数量大于ECC解码器可以纠正的最大错误数量，则该方法生成修改后的码字，计算修正码字的校正效果，并根据校正效果确定解码码字。