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公开(公告)号：US08978077B2
公开(公告)日：2015-03-10
申请号：US12390828
申请日：2009-02-23
申请人： Constantine Elster , Ron Keidar , Nela Gurevich , Stephen Verrall
发明人： Constantine Elster , Ron Keidar , Nela Gurevich , Stephen Verrall
IPC分类号： H04N7/173 , H04N21/234 , H04N21/432 , H04N21/438 , H04N21/44
CPC分类号： H04N21/23406 , H04N21/4325 , H04N21/4384 , H04N21/44004
摘要： Systems and methods to present video content are disclosed. According to an embodiment, a method of processing video data is disclosed. The method includes receiving timing information associated with the video data. The received timing information is indicative of a start time to start presentation of video content corresponding to the video data. The method includes starting presentation of the video content at a time prior to the start time. The method also includes increasing a presentation rate of the video content.
摘要翻译： 公开了呈现视频内容的系统和方法。 根据实施例，公开了一种处理视频数据的方法。 该方法包括接收与视频数据相关联的定时信息。 所接收的定时信息表示开始显示对应于视频数据的视频内容的开始时间。 该方法包括在开始时间之前开始显示视频内容。 该方法还包括增加视频内容的呈现速率。
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公开(公告)号：US20100266050A1
公开(公告)日：2010-10-21
申请号：US12427479
申请日：2009-04-21
申请人： Ron Keidar , Nela Gurevich , Constantine Elster
发明人： Ron Keidar , Nela Gurevich , Constantine Elster
CPC分类号： H04H20/40 , H04H20/18 , H04N21/4305
摘要： A system and method for decoding multimedia video is described. Particularly, a system and method for determining the time of arrival of packets, without a hardware interface, is disclosed. As described herein, the time of arrival for each packet may be derived by extrapolating information from the arrival of a frame boundary and the specifications of the transmission standard. This permits the calculation of drift between the encoder and decoder clocks and consequently the more accurate decoding of the transmission.
摘要翻译： 描述用于解码多媒体视频的系统和方法。 特别地，公开了一种用于在没有硬件接口的情况下确定分组的到达时间的系统和方法。 如本文所述，每个分组的到达时间可以通过从帧边界的到达和传输标准的规范的外推来推导出来。 这允许计算编码器和解码器时钟之间的漂移，从而更准确地解码传输。
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公开(公告)号：US08396133B2
公开(公告)日：2013-03-12
申请号：US12427479
申请日：2009-04-21
申请人： Ron Keidar , Nela Gurevich , Constantine Elster
发明人： Ron Keidar , Nela Gurevich , Constantine Elster
CPC分类号： H04H20/40 , H04H20/18 , H04N21/4305
摘要： A system and method for decoding multimedia video is described. Particularly, a system and method for determining the time of arrival of packets, without a hardware interface, is disclosed. As described herein, the time of arrival for each packet may be derived by extrapolating information from the arrival of a frame boundary and the specifications of the transmission standard. This permits the calculation of drift between the encoder and decoder clocks and consequently the more accurate decoding of the transmission.
摘要翻译： 描述用于解码多媒体视频的系统和方法。 特别地，公开了一种用于在没有硬件接口的情况下确定分组的到达时间的系统和方法。 如本文所述，每个分组的到达时间可以通过从帧边界的到达和传输标准的规范的外推来推导出来。 这允许计算编码器和解码器时钟之间的漂移，从而更准确地解码传输。
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公开(公告)号：US20100218226A1
公开(公告)日：2010-08-26
申请号：US12390828
申请日：2009-02-23
申请人： Constantine Elster , Ron Keidar , Neia Gurevich , Stephen Verrall
发明人： Constantine Elster , Ron Keidar , Neia Gurevich , Stephen Verrall
IPC分类号： H04N7/173
CPC分类号： H04N21/23406 , H04N21/4325 , H04N21/4384 , H04N21/44004
摘要： Systems and methods to present video content are disclosed. According to an embodiment, a method of processing video data is disclosed. The method includes receiving timing information associated with the video data. The received timing information is indicative of a start time to start presentation of video content corresponding to the video data. The method includes starting presentation of the video content at a time prior to the start time. The method also includes increasing a presentation rate of the video content.
摘要翻译： 公开了呈现视频内容的系统和方法。 根据实施例，公开了一种处理视频数据的方法。 该方法包括接收与视频数据相关联的定时信息。 所接收的定时信息表示开始显示对应于视频数据的视频内容的开始时间。 该方法包括在开始时间之前开始显示视频内容。 该方法还包括增加视频内容的呈现速率。
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公开(公告)号：US08700105B2
公开(公告)日：2014-04-15
申请号：US12020389
申请日：2008-01-25
CPC分类号： H04W52/0216 , H04W4/14 , H04W52/0235 , H04W52/0248 , H04W72/12 , H04W88/02 , Y02D70/122 , Y02D70/142 , Y02D70/144 , Y02D70/162 , Y02D70/164
摘要： The subject matter disclosed herein relates to a system and method for establishing communication between a low duty cycle device and other devices through a wireless communication network. In one particular implementation, the low duty cycle device may awaken from a hibernating state in synchronization with transmission of messages.
摘要翻译： 本文公开的主题涉及通过无线通信网络建立低占空比装置与其他装置之间的通信的系统和方法。 在一个特定实现中，低占空比设备可以与消息的传输同步地从休眠状态唤醒。
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公开(公告)号：US20130132735A1
公开(公告)日：2013-05-23
申请号：US13467853
申请日：2012-05-09
IPC分类号： G06F12/14
CPC分类号： G06F12/1408 , G06F21/62 , G06F21/6218 , G06F21/79 , G06F2221/2113
摘要： Disclosed is a processor for processing data from a buffer memory. The processor, implemented in hardware, may allow writing of output data, processed based on input data from at least one secure location associated with a secure address range of the buffer memory, to one or more secure locations associated with the secure address range. Further, the processor may block writing of output data, processed based on input data from at least one secure location associated with the secure address range, to one or more insecure locations associated with an insecure address range of the buffer memory.
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公开(公告)号：US08218568B2
公开(公告)日：2012-07-10
申请号：US12172116
申请日：2008-07-11
申请人： Ron Keidar , Eitan Yacobi , Haim Weissmann
发明人： Ron Keidar , Eitan Yacobi , Haim Weissmann
摘要： An apparatus and method for synchronizing RF activities comprising receiving a notification relating to transmission activities; determining at least one of a plurality of RF modules to relay the notification; and relaying the notification to at least one of the plurality of RF modules.
摘要翻译： 一种用于同步RF活动的装置和方法，包括接收与传输活动相关的通知; 确定多个RF模块中的至少一个来中继所述通知; 以及将所述通知中继到所述多个RF模块中的至少一个。
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公开(公告)号：US20100008336A1
公开(公告)日：2010-01-14
申请号：US12172116
申请日：2008-07-11
申请人： Ron Keidar , Eitan Jacobi , Haim Weissman
发明人： Ron Keidar , Eitan Jacobi , Haim Weissman
摘要： An apparatus and method for synchronizing RF activities comprising receiving a notification relating to transmission activities; determining at least one of a plurality of RF modules to relay the notification; and relaying the notification to at least one of the plurality of RF modules.
摘要翻译： 一种用于同步RF活动的装置和方法，包括接收与传输活动相关的通知; 确定多个RF模块中的至少一个来中继所述通知; 以及将所述通知中继到所述多个RF模块中的至少一个。
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9.发明授权公开(公告)号：US08432941B2
公开(公告)日：2013-04-30
申请号：US12477782
申请日：2009-06-03
申请人： Ron Keidar
发明人： Ron Keidar
CPC分类号： H04N21/64315 , H04H20/426 , H04N5/50 , H04N21/41407 , H04N21/4384 , H04N21/44004
摘要： Embodiments relate to systems and methods for the selective caching of burst stream transmissions. A digital video (e.g., DVB-H) or other transport stream can be received on a cellular telephone or other device. The transport stream can be divided into bursts in a sequence of cyclical time slots, each slot carrying one service such as a video channel. The bursts contained in the time slots most distant in time from a currently received time slot can be stored to an onboard cache. When a user wishes to change the service being played, they can select the new desired service. If the user chooses to switch or “zap” to one of the cached services, the media decoder on the device can immediately begin decoding and playing the service encoded in that burst back, rather than waiting for the arrival of the next time slot of the subsequent burst for that service.
摘要翻译： 实施例涉及用于突发流传输的选择性缓存的系统和方法。 数字视频（例如，DVB-H）或其他传输流可以在蜂窝电话或其他设备上接收。 传输流可以以循环时隙的序列划分为突发，每个时隙承载一个服务，例如视频信道。 包含在距当前接收的时隙的时间最远的时隙中的突发可以被存储到板载高速缓存。 当用户希望改变正在播放的服务时，他们可以选择新的所需服务。 如果用户选择切换或“切换”到缓存服务之一，设备上的媒体解码器可以立即开始解码和播放在该突发中编码的服务，而不是等待下一个时隙的到达 随后突发这项服务。
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10.发明申请APPARATUS AND METHOD FOR HARDWARE-BASED SECURE DATA PROCESSING USING BUFFER MEMORY ADDRESS RANGE RULES 有权使用缓冲存储器地址范围规则进行硬件安全数据处理的装置和方法公开(公告)号：US20150106630A1
公开(公告)日：2015-04-16
申请号：US14572520
申请日：2014-12-16
CPC分类号： G06F12/1408 , G06F21/62 , G06F21/6218 , G06F21/79 , G06F2221/2113
摘要： Disclosed is a processor for processing data from a buffer memory. The processor, implemented in hardware, may allow writing of output data, processed based on input data from at least one secure location associated with a secure address range of the buffer memory, to one or more secure locations associated with the secure address range. Further, the processor may block writing of output data, processed based on input data from at least one secure location associated with the secure address range, to one or more insecure locations associated with an insecure address range of the buffer memory.
摘要翻译： 公开了一种用于处理来自缓冲存储器的数据的处理器。 以硬件实现的处理器可以允许将基于与缓冲存储器的安全地址范围相关联的至少一个安全位置的输入数据处理的输出数据写入与安全地址范围相关联的一个或多个安全位置。 此外，处理器可以将与基于与安全地址范围相关联的至少一个安全位置的输入数据处理的输出数据写入到与缓冲存储器的不安全地址范围相关联的一个或多个不安全位置。
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