利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

32 条记录 (耗时 0.028 秒)

    Circuit arrangement and method incorporating data buffer with priority-based data storage
    1.
    发明授权
    Circuit arrangement and method incorporating data buffer with priority-based data storage 失效
    具有基于优先级的数据存储的数据缓冲器的电路布置和方法

    公开(公告)号：US06260090B1

    公开(公告)日：2001-07-10

    申请号：US09262158

    申请日：1999-03-03

    申请人： Ronald Edward Fuhs ,  Kenneth Claude Hinz ,  Russell Dean Hoover ,  David Alan Shedivy

    发明人： Ronald Edward Fuhs ,  Kenneth Claude Hinz ,  Russell Dean Hoover ,  David Alan Shedivy

    IPC分类号： G06F1300

    CPC分类号： G06F13/18

    摘要： A data processing system, circuit arrangement, integrated circuit device, program product, and method utilize a data buffer with a priority-based data storage capability to handle incoming data from a plurality of available data sources. With such a capability, different relative priority levels are assigned to data associated with different data sources. Such priority levels are then used by control logic coupled to the buffer to control whether or not incoming data is stored (or optionally discarded) in the buffer. In particular, the relative priority of incoming data is compared with that associated with data currently stored in the buffer, with the incoming data being stored in the buffer only when its relative priority exceeds that of the currently-stored data.

    摘要翻译： 数据处理系统，电路装置，集成电路装置，程序产品和方法利用具有基于优先级的数据存储能力的数据缓冲器来处理来自多个可用数据源的输入数据。 利用这样的能力，将不同的相对优先级分配给与不同数据源相关联的数据。 这样的优先级然后被耦合到缓冲器的控制逻辑使用，以控制是否在缓冲器中存储（或可选地丢弃）输入数据。 特别地，将输入数据的相对优先级与与当前存储在缓冲器中的数据相关联的输入数据的相对优先级进行比较，其中输入数据仅在其相对优先级超过当前存储的数据的情况下存储在缓冲器中。

    Ordering mechanism, ordering method and computer program product for implementing PCI peer to functions
    2.
    发明授权
    Ordering mechanism, ordering method and computer program product for implementing PCI peer to functions 失效
    用于实现PCI对等功能的订购机制，订购方法和计算机程序产品

    公开(公告)号：US06529991B1

    公开(公告)日：2003-03-04

    申请号：US09310797

    申请日：1999-05-12

    申请人： Bruce Leroy Beukema ,  Ronald Edward Fuhs ,  Kenneth Claude Hinz

    发明人： Bruce Leroy Beukema ,  Ronald Edward Fuhs ,  Kenneth Claude Hinz

    IPC分类号： G06F1320

    CPC分类号： G06F13/423 ,  G06F13/1621

    摘要： An ordering mechanism, ordering method and computer program product are provided for implementing PCI local bus (PCI) peer to peer functions. When a read command is received, checking for available resource is performed. Responsive to not identifying available resource, a retry read command is sent. Responsive to sending the read command; checking for the retry read received command is provided. Responsive to identifying the retry read received command, the read command is resent.

    摘要翻译： 提供了一种用于实现PCI局部总线（PCI）对等功能的排序机制，排序方法和计算机程序产品。 当接收到读命令时，执行检查可用资源。 响应于不识别可用资源，发送重试读取命令。 响应发送读命令; 提供检查重试读取命令。 响应于识别重试读取命令，读取命令被重新发送。

    Apparatus and method for tracking packets in a reliably connected transmission system
    6.
    发明授权
    Apparatus and method for tracking packets in a reliably connected transmission system 失效
    在可靠连接的传输系统中跟踪数据包的装置和方法

    公开(公告)号：US07328390B2

    公开(公告)日：2008-02-05

    申请号：US11734690

    申请日：2007-04-12

    申请人： Ronald Edward Fuhs ,  Steven Lyn Rogers ,  Nathaniel Paul Sellin ,  Scott Michael Willenborg

    发明人： Ronald Edward Fuhs ,  Steven Lyn Rogers ,  Nathaniel Paul Sellin ,  Scott Michael Willenborg

    IPC分类号： G08C25/02 ,  H04L1/18

    CPC分类号： H04L49/901 ,  H04L1/16 ,  H04L1/188 ,  H04L49/90

    摘要： A method and apparatus tracks packets and reliably transmits data over a computer transmission system with a reduced amount of memory needed in the transmission interface. The invention eliminates the need to keep all the packets of data queued until the acknowledge message for that data has arrived. Instead, it keeps track of how many packets have been sent and which packets correspond to the end of a message, marking them off when acknowledge messages are received. If packets are lost, the invention determines which packet were lost, backs up to the lost packet, re-fetches the data and resends it. Embodiments of the present invention eliminate the need to queue packets, reducing silicon size and allowing the available bandwidth of the output bus to be more fully utilized.

    摘要翻译： 一种方法和装置跟踪分组并通过计算机传输系统可靠地传输数据，传输接口中所需的存储器数量减少。 本发明消除了在数据的确认消息到达之前排队所有数据包的需要。 相反，它跟踪已经发送了多少个数据包，哪些数据包对应于消息的结尾，在接收到确认消息时将它们标记出来。 如果分组丢失，则本发明确定哪个分组丢失，备份到丢失的分组，重新获取数据并重新发送。 本发明的实施例消除了对分组进行排队的需要，减小了硅尺寸并且允许更充分地利用输出总线的可用带宽。

    Method for implementing dynamic virtual lane buffer reconfiguration
    7.
    发明授权
    Method for implementing dynamic virtual lane buffer reconfiguration 失效
    实现动态虚拟通道缓冲区重新配置的方法

    公开(公告)号：US07188198B2

    公开(公告)日：2007-03-06

    申请号：US10660033

    申请日：2003-09-11

    申请人： Bruce Leroy Beukema ,  Ronald Edward Fuhs ,  Calvin Charles Paynton ,  Steven Lyn Rogers ,  Bruce Marshall Walk

    发明人： Bruce Leroy Beukema ,  Ronald Edward Fuhs ,  Calvin Charles Paynton ,  Steven Lyn Rogers ,  Bruce Marshall Walk

    IPC分类号： G06F3/00

    CPC分类号： H04L47/30 ,  H04L49/35 ,  H04L49/358 ,  H04L49/90 ,  H04L49/9078

    摘要： A method, apparatus and computer program product are provided for implementing dynamic Virtual Lane buffer reconfiguration in a channel adapter. A first register is provided for communicating an adapter buffer size and allocation capability for the channel adapter. At least one second register is provided for communicating a current port buffer size and one second register is associated with each physical port of the channel adapter. A plurality of third registers is provided for communicating a current VL buffer size, and one third register is associated with each VL of each physical port of the channel adapter. The second register is used for receiving change requests for adjusting the current port buffer size for an associated physical port. The third register is used for receiving change requests for adjusting the current VL buffer size for an associated VL.

    摘要翻译： 提供了一种用于在通道适配器中实现动态虚拟通道缓冲器重新配置的方法，装置和计算机程序产品。 第一个寄存器用于传送适配器缓冲区大小和通道适配器的分配能力。 提供至少一个第二寄存器用于传送当前端口缓冲器大小，一个第二寄存器与信道适配器的每个物理端口相关联。 提供多个第三寄存器用于传送当前的VL缓冲器大小，并且一个第三寄存器与通道适配器的每个物理端口的每个VL相关联。 第二个寄存器用于接收用于调整相关物理端口的当前端口缓冲区大小的更改请求。 第三寄存器用于接收用于调整相关VL的当前VL缓冲器大小的改变请求。

    Apparatus, system and method for controlling access to facilities based on usage classes
    8.
    发明授权
    Apparatus, system and method for controlling access to facilities based on usage classes 有权
    基于使用类别控制对设施的访问的装置，系统和方法

    公开(公告)号：US07010633B2

    公开(公告)日：2006-03-07

    申请号：US10411447

    申请日：2003-04-10

    申请人： Richard Louis Arndt ,  Bruce Leroy Beukema ,  David F. Craddock ,  Ronald Edward Fuhs ,  Thomas Anthony Gregg ,  Bruce Marshall Walk

    发明人： Richard Louis Arndt ,  Bruce Leroy Beukema ,  David F. Craddock ,  Ronald Edward Fuhs ,  Thomas Anthony Gregg ,  Bruce Marshall Walk

    IPC分类号： G06F13/14 ,  G06F15/173

    CPC分类号： G06F12/1491

    摘要： An apparatus, system and method for controlling access to facilities based on usage class of a requestor are provided. With the apparatus, system and method, a two level protection mechanism is provided for protecting host channel adapter (HCA) facilities from unauthorized access. With the present invention, a first level of access is provided through virtual address translation and a mechanism for determining if the requestor of access may access a system memory address space page associated with a real address to which the virtual address maps. A second level of access is provided through the allocation of usage classes and determining a required usage class for accessing an HCA facility.

    摘要翻译： 提供了一种用于基于请求者的使用类来控制对设施的访问的装置，系统和方法。 利用设备，系统和方法，提供了一种保护主机通道适配器（HCA）设施免受未经授权访问的两级保护机制。 利用本发明，通过虚拟地址转换提供第一级别的访问，以及用于确定访问请求者是否可访问与虚拟地址映射到的实际地址相关联的系统存储器地址空间页面的机制。 通过分配使用类别并确定访问HCA设施所需的使用类别来提供第二级别的访问。