专利检索 ap:("Ronald G. Filippi, Jr." OR "Giovanni Fiorenza" OR "Xiao Hu Liu" OR "Conal Eugene Murray" OR "Gregory Allen Northrop" OR "Thomas M. Shaw" OR "Richard Andre′ Wachnik" OR "Mary Yvonne Lanzerotti Wisniewski") AND inv:"Richard Andre′ Wachnik" 第 1 页

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发明授权
Method of extracting properties of back end of line (BEOL) chip architecture 失效
标题翻译：提取后端（BEOL）芯片架构性能的方法

公开(公告)号：US07260810B2

公开(公告)日：2007-08-21

申请号：US10687475

申请日：2003-10-16

申请人： Ronald G. Filippi, Jr. , Giovanni Fiorenza , Xiao Hu Liu , Conal Eugene Murray , Gregory Allen Northrop , Thomas M. Shaw , Richard Andre′ Wachnik , Mary Yvonne Lanzerotti Wisniewski

发明人： Ronald G. Filippi, Jr. , Giovanni Fiorenza , Xiao Hu Liu , Conal Eugene Murray , Gregory Allen Northrop , Thomas M. Shaw , Richard Andre′ Wachnik , Mary Yvonne Lanzerotti Wisniewski

IPC分类号： G06F17/50 , G03F1/00

CPC分类号： G06F17/5018

摘要： A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each pixel element representing a portion of the design. Then, a response of the design is determined due to local properties across the design.

摘要翻译： 用于分析电路设计的方法包括将设计表示离散成代表设计中的结构的像素元素，并且为表示设计的一部分的每个像素元素确定至少一个属性。然后，由于设计中的局部属性，确定了设计的响应。