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    Method and apparatus for accelerated determination of electromigration characteristics of semiconductor wiring
    2.
    发明授权
    Method and apparatus for accelerated determination of electromigration characteristics of semiconductor wiring 失效
    用于加速确定半导体布线的电迁移特性的方法和装置

    公开(公告)号：US06603321B2

    公开(公告)日：2003-08-05

    申请号：US09999719

    申请日：2001-10-26

    申请人： Ronald G. Filippi, Jr. ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Deborah Tibel ,  Michael Ruprecht ,  Carole Graas

    发明人： Ronald G. Filippi, Jr. ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Deborah Tibel ,  Michael Ruprecht ,  Carole Graas

    IPC分类号： G01R3126

    CPC分类号： H01L22/34 ,  G01R31/2858 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A method for determining the electromigration characteristics of a wiring structure in an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes configuring a defined test structure type for the integrated circuit device. The defined test structure type further includes a first line of wiring primarily disposed in a principal plane of a semiconductor substrate, and a second line of wiring connected to the first line of wiring. The second line of wiring is disposed in a secondary plane which is substantially parallel to the principal plane, with the first and second lines of wiring being connected by a via structure therebetween. A thermal coefficient of resistance for the first line of wiring and the via structure is determined, and a wafer-level stress condition is introduced in a first individual test structure of the defined test structure type. Then, at least one parameter value for is determined for the first individual test structure, which parameter value is used to predict a lifetime projection for the wiring structure in the integrated circuit device.

    摘要翻译： 公开了一种用于确定集成电路器件中的布线结构的电迁移特性的方法。 在本发明的示例性实施例中，该方法包括配置用于集成电路器件的定义的测试结构类型。 所确定的测试结构类型还包括主要布置在半导体衬底的主平面中的第一布线和连接到第一布线的第二布线。 布线的第二线设置在基本上平行于主平面的二次平面中，其中第一和第二布线通过它们之间的通孔结构连接。 确定第一线路和通孔结构的电阻的热系数，并且在限定的测试结构类型的第一单独测试结构中引入晶片级应力条件。 然后，对于第一单独测试结构确定至少一个参数值，哪个参数值用于预测集成电路器件中的布线结构的寿命投影。

    Apparatus and method for testing semiconductors
    3.
    发明授权
    Apparatus and method for testing semiconductors 失效
    用于半导体测试的装置和方法

    公开(公告)号：US06836106B1

    公开(公告)日：2004-12-28

    申请号：US10668561

    申请日：2003-09-23

    申请人： Kevin H. Brelsford ,  Ronald G. Filippi, Jr. ,  Kenneth P. Rodbell ,  Ping-Chuan Wang

    发明人： Kevin H. Brelsford ,  Ronald G. Filippi, Jr. ,  Kenneth P. Rodbell ,  Ping-Chuan Wang

    IPC分类号： G01R3126

    CPC分类号： G11C29/56 ,  G01R31/2858 ,  G11C29/1201 ,  G11C2029/5602

    摘要： A test circuit for testing semiconductors includes a plurality of at least first conductors and second conductors. The first and second conductors are operatively connected together by a plurality of conductive vias to form an open chain of alternating first and second conductors. A plurality of conductive taps are included, each of the taps being connected at a first end to a corresponding first conductor. The test circuit further includes a plurality of switching circuits, each of the switching circuits being operatively connected to a second end of a corresponding one of the conductive taps. Each of the switching circuits is configurable for selectively connecting the corresponding conductive tap to one of at least a first bus and a second bus in response to at least one control signal presented to the switching circuit, the first and second buses being connected to first and second bond pads, respectively.

    摘要翻译： 用于测试半导体的测试电路包括多个至少第一导体和第二导体。 第一和第二导体通过多个导电通孔可操作地连接在一起以形成交替的第一和第二导体的开链。 包括多个导电抽头，每个抽头在第一端连接到对应的第一导体。 测试电路还包括多个开关电路，每个开关电路可操作地连接到对应的一个导电抽头的第二端。 响应于呈现给开关电路的至少一个控制信号，每个开关电路可配置为有选择地将对应的导电抽头连接到至少第一总线和第二总线中的一个，第一和第二总线连接到第一和第二总线 第二接合垫。