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1.发明授权公开(公告)号：US07260810B2
公开(公告)日：2007-08-21
申请号：US10687475
申请日：2003-10-16
申请人： Ronald G. Filippi, Jr. , Giovanni Fiorenza , Xiao Hu Liu , Conal Eugene Murray , Gregory Allen Northrop , Thomas M. Shaw , Richard Andre′ Wachnik , Mary Yvonne Lanzerotti Wisniewski
发明人： Ronald G. Filippi, Jr. , Giovanni Fiorenza , Xiao Hu Liu , Conal Eugene Murray , Gregory Allen Northrop , Thomas M. Shaw , Richard Andre′ Wachnik , Mary Yvonne Lanzerotti Wisniewski
CPC分类号： G06F17/5018
摘要： A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each pixel element representing a portion of the design. Then, a response of the design is determined due to local properties across the design.
摘要翻译： 用于分析电路设计的方法包括将设计表示离散成代表设计中的结构的像素元素，并且为表示设计的一部分的每个像素元素确定至少一个属性。 然后，由于设计中的局部属性，确定了设计的响应。
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公开(公告)号：US06989282B2
公开(公告)日：2006-01-24
申请号：US10815418
申请日：2004-04-01
申请人： Ronald Gene Filippi , Lynne Marie Gignac , Vincent J. McGahay , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
发明人： Ronald Gene Filippi , Lynne Marie Gignac , Vincent J. McGahay , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC分类号： H01L21/66
CPC分类号： G01R31/2881
摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.
摘要翻译： 公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。 在结构中感兴趣的位置确定菌株。 在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。 基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。 可以根据结果进行预测和设计更改。
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公开(公告)号：US20080224135A1
公开(公告)日：2008-09-18
申请号：US12128260
申请日：2008-05-28
申请人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang , Conal Eugene Murray
发明人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang , Conal Eugene Murray
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
摘要翻译： 用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。 测试结构热循环，测量结构的产量。 基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。
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公开(公告)号：US09287186B2
公开(公告)日：2016-03-15
申请号：US12128260
申请日：2008-05-28
申请人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
发明人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
CPC分类号： H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
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公开(公告)号：US07388224B2
公开(公告)日：2008-06-17
申请号：US11502196
申请日：2006-08-10
申请人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
发明人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
摘要翻译： 用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。 测试结构热循环，测量结构的产量。 基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。
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公开(公告)号：US07098054B2
公开(公告)日：2006-08-29
申请号：US10783462
申请日：2004-02-20
申请人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
发明人： Ronald Gene Filippi , Jason Paul Gill , Vincent J. McGahay , Paul Stephen McLaughlin , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
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公开(公告)号：US07345305B2
公开(公告)日：2008-03-18
申请号：US11248719
申请日：2005-10-12
申请人： Ronald Gene Filippi , Lynne Marie Gignac , Vincent J. McGahay , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
发明人： Ronald Gene Filippi , Lynne Marie Gignac , Vincent J. McGahay , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC分类号： H01L23/58
CPC分类号： G01R31/2881
摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.
摘要翻译： 公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。 在结构中感兴趣的位置确定菌株。 在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。 基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。 可以根据结果进行预测和设计更改。
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8.发明申请Compressive (PFET) and Tensile (NFET) Channel Strain in Nanowire FETs Fabricated with a Replacement Gate Process 有权用替代栅极工艺制造的纳米线FET中的压电（PFET）和拉伸（NFET）通道应变公开(公告)号：US20130175503A1
公开(公告)日：2013-07-11
申请号：US13344352
申请日：2012-01-05
IPC分类号： H01L29/775 , H01L21/336 , B82Y99/00 , B82Y40/00
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/66439
摘要： A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.
摘要翻译： 提供一种制造FET器件的方法，其包括以下步骤。 纳米线/焊盘形成在BOX层上的SOI层中，其中纳米线悬挂在BOX上。 沉积围绕纳米线的HSQ层。 围绕纳米线的HSQ层的一部分交联，其中交联导致HSQ层的一部分收缩，从而诱导纳米线中的应变。 形成一个或多个保持在纳米线中诱发的应变的栅极。 还提供了一种FET器件，其中每个纳米线具有变形的第一区域，使得第一区域中的晶格常数小于纳米线的松弛晶格常数和第二区域， 其变形使得第二区域中的晶格常数大于纳米线的松弛晶格常数。
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9.发明授权Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process 有权用替代栅极工艺制造的纳米线FET中的压电（PFET）和拉伸（NFET）沟道应变公开(公告)号：US08492208B1
公开(公告)日：2013-07-23
申请号：US13344352
申请日：2012-01-05
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/66439
摘要： A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.
摘要翻译： 提供一种制造FET器件的方法，其包括以下步骤。 纳米线/焊盘形成在BOX层上的SOI层中，其中纳米线悬挂在BOX上。 沉积围绕纳米线的HSQ层。 围绕纳米线的HSQ层的一部分交联，其中交联导致HSQ层的一部分收缩，从而诱导纳米线中的应变。 形成一个或多个保持在纳米线中诱发的应变的栅极。 还提供了一种FET器件，其中每个纳米线具有变形的第一区域，使得第一区域中的晶格常数小于纳米线的松弛晶格常数和第二区域， 其变形使得第二区域中的晶格常数大于纳米线的松弛晶格常数。
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10.发明申请SCHOTTKY BARRIER SOLAR CELLS WITH HIGH AND LOW WORK FUNCTION METAL CONTACTS 审中-公开SCHOTTKY BARRIER太阳能电池具有高低功能金属接触公开(公告)号：US20120285517A1
公开(公告)日：2012-11-15
申请号：US13103490
申请日：2011-05-09
申请人： Joel P. de Souza , Harold John Hovel , Daniel Inns , Jeehwan Kim , Christian Lavoie , Conal Eugene Murray , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi , Davood Shahrjerdi , Zhen Zhang
发明人： Joel P. de Souza , Harold John Hovel , Daniel Inns , Jeehwan Kim , Christian Lavoie , Conal Eugene Murray , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi , Davood Shahrjerdi , Zhen Zhang
IPC分类号： H01L31/108 , H01L31/18
CPC分类号： H01L31/07 , H01L31/0321 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A Schottky Barrier solar cell having at least one of a low work function region and a high work function region provided on the front or back surface of a lightly-doped absorber material, which may be produced in a variety of different geometries. The method of producing the Schottky Barrier solar cells allows for short processing times and the use of low temperatures.
摘要翻译： 一种肖特基势垒太阳能电池，其具有设置在轻掺杂的吸收材料的前表面或后表面上的低功函数区域和高功函数区域中的至少一个，其可以以各种不同的几何形状生产。 生产肖特基势垒太阳能电池的方法允许短的处理时间和低温的使用。
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