公开(公告)号：US20110022800A1

公开(公告)日：2011-01-27

申请号：US12934275

申请日：2008-04-11

申请人： Rotem Porat ,  Moshe Anschel ,  Alon Eldar ,  Amit Gur ,  Shai Koren ,  Itay Peled

发明人： Rotem Porat ,  Moshe Anschel ,  Alon Eldar ,  Amit Gur ,  Shai Koren ,  Itay Peled

IPC分类号： G06F12/08

CPC分类号： G06F12/0864 ,  G06F12/126

摘要： A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way.

摘要翻译： 一种用于选择高速缓存方式的方法，所述方法包括：从用于接收数据单元的高速缓存模块的多个高速缓存路径中选择最初选择的高速缓存路; 所述方法的特征在于包括：从位于与所述第一高速缓存方式预定义的偏移量的至少一组高速缓存路径中，搜索所述初始选择的高速缓存方式是否被锁定，以解锁的高速缓存方式。

公开(公告)号：US08832378B2

公开(公告)日：2014-09-09

申请号：US12934275

申请日：2008-04-11

申请人： Rotem Porat ,  Moshe Anschel ,  Alon Eldar ,  Amit Gur ,  Shai Koren ,  Itay Peled

发明人： Rotem Porat ,  Moshe Anschel ,  Alon Eldar ,  Amit Gur ,  Shai Koren ,  Itay Peled

IPC分类号： G06F12/00 ,  G06F12/12 ,  G06F12/08

CPC分类号： G06F12/0864 ,  G06F12/126

摘要： A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way.

摘要翻译： 一种用于选择高速缓存方式的方法，所述方法包括：从用于接收数据单元的高速缓存模块的多个高速缓存路径中选择最初选择的高速缓存路; 所述方法的特征在于包括：从位于与所述第一高速缓存方式预定义的偏移量的至少一组高速缓存路径中，搜索所述初始选择的高速缓存方式是否被锁定，以解锁的高速缓存方式。

公开(公告)号：US20090063779A1

公开(公告)日：2009-03-05

申请号：US11849375

申请日：2007-09-04

申请人： Shai Koren ,  Alon Eldar ,  Amit Gur ,  Itay Peled ,  Rotem Porat

发明人： Shai Koren ,  Alon Eldar ,  Amit Gur ,  Itay Peled ,  Rotem Porat

IPC分类号： G06F12/08

CPC分类号： G06F12/0857 ,  G06F12/0846 ,  G06F12/0855 ,  G06F2212/1012

摘要： A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a sequence of pipeline stages, the sequence comprises an input pipeline stage that is connected to the arbiter; and (iii) multiple cache resources, connected to the sequence of pipeline stages; wherein each cache resource can be read only by a small portion of the sequence of pipeline stages and can be written to only by a small portion of the sequence of pipeline stages.

摘要翻译： 一种高速缓冲存储器，包括：（i）连接到多址接入发生器的仲裁器，所述仲裁器适于从多个接入发生器接收不同类型的接入请求，并且每个仲裁周期选择单个接入请求; （ii）流水线级序列，该序列包括连接到仲裁器的输入流水线级; 和（iii）连接到流水线级序列的多个高速缓存资源; 其中每个高速缓存资源只能由流水线级的序列的一小部分读取，并且可以仅被写入流水线级序列的一小部分。

公开(公告)号：US08103833B2

公开(公告)日：2012-01-24

申请号：US11849375

申请日：2007-09-04

申请人： Shai Koren ,  Alon Eldar ,  Amit Gur ,  Itay Peled ,  Rotem Porat

发明人： Shai Koren ,  Alon Eldar ,  Amit Gur ,  Itay Peled ,  Rotem Porat

IPC分类号： G06F12/00

CPC分类号： G06F12/0857 ,  G06F12/0846 ,  G06F12/0855 ,  G06F2212/1012

摘要： A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a sequence of pipeline stages, the sequence comprises an input pipeline stage that is connected to the arbiter; and (iii) multiple cache resources, connected to the sequence of pipeline stages; wherein each cache resource can be read only by a small portion of the sequence of pipeline stages and can be written to only by a small portion of the sequence of pipeline stages.

摘要翻译： 一种高速缓冲存储器，包括：（i）连接到多址接入发生器的仲裁器，所述仲裁器适于从多个接入发生器接收不同类型的接入请求，并且每个仲裁周期选择单个接入请求; （ii）流水线级序列，该序列包括连接到仲裁器的输入流水线级; 和（iii）连接到流水线级序列的多个高速缓存资源; 其中每个高速缓存资源只能由流水线级的序列的一小部分读取，并且可以仅被写入流水线级序列的一小部分。

公开(公告)号：US08886895B2

公开(公告)日：2014-11-11

申请号：US10940121

申请日：2004-09-14

申请人： Itay Peled ,  Moshe Anschel ,  Jacob Efrat ,  Alon Eldar ,  Ziv Zamsky

发明人： Itay Peled ,  Moshe Anschel ,  Jacob Efrat ,  Alon Eldar ,  Ziv Zamsky

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0859 ,  G06F12/0862

摘要： A method for fetching information in response to hazard indication information, the method includes: (i) associating hazard indication information to at least one information unit that is being fetched to the cache module; (ii) receiving a request to perform a fetch operation; and (iii) determining whether to fetch at least one information unit to the cache module in response to the hazard indication information and in response to dirty information associated with the at least one information unit.

摘要翻译： 一种用于响应于危险指示信息获取信息的方法，所述方法包括：（i）将危险指示信息与被提取到所述缓存模块的至少一个信息单元相关联; （ii）接收执行取出操作的请求; 以及（iii）响应于所述危险指示信息以及响应于与所述至少一个信息单元相关联的脏信息，确定是否将至少一个信息单元提取给所述高速缓存模块。

公开(公告)号：US08117400B2

公开(公告)日：2012-02-14

申请号：US12446413

申请日：2006-10-20

申请人： Ziv Zamsky ,  Moshe Anschel ,  Alon Eldar ,  Dmitry Flat ,  Kostantin Godin ,  Itay Peled ,  Dvir Peleg

发明人： Ziv Zamsky ,  Moshe Anschel ,  Alon Eldar ,  Dmitry Flat ,  Kostantin Godin ,  Itay Peled ,  Dvir Peleg

IPC分类号： G06F12/00

CPC分类号： G06F12/0859 ,  G06F9/3834 ,  G06F12/0862

摘要： A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining, when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing the information unit to the cache module in response to the cache module in response to the determination.

摘要翻译： 一种用于获取信息单元的设备和方法，所述方法包括：通过所述信息单元的可高速缓存操作来接收执行写入的请求; 从数据中取出取出单元，其中取出单元连接到高速缓存模块和高级存储单元; 当所述提取单元为空时，确定所述高速缓存模块是否存储所述信息单元的旧版本; 以及响应于所述确定而响应于所述高速缓存模块选择性地将所述信息单元写入所述高速缓存模块。

公开(公告)号：US20100325366A1

公开(公告)日：2010-12-23

申请号：US12446413

申请日：2006-10-20

申请人： Ziv Zamsky ,  Moshe Anschel ,  Alon Eldar ,  Dmitry Flat ,  Kostantin Godin ,  Itay Peled ,  Dvir Peleg

发明人： Ziv Zamsky ,  Moshe Anschel ,  Alon Eldar ,  Dmitry Flat ,  Kostantin Godin ,  Itay Peled ,  Dvir Peleg

IPC分类号： G06F12/08

CPC分类号： G06F12/0859 ,  G06F9/3834 ,  G06F12/0862

摘要： A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining, when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing the information unit to the cache module in response to the cache module in response to the determination.

摘要翻译： 一种用于获取信息单元的设备和方法，所述方法包括：通过所述信息单元的可高速缓存操作来接收执行写入的请求; 从数据中取出取出单元，其中取出单元连接到高速缓存模块和高级存储单元; 当所述提取单元为空时，确定所述高速缓存模块是否存储所述信息单元的旧版本; 以及响应于所述确定而响应于所述高速缓存模块选择性地将所述信息单元写入所述高速缓存模块。

公开(公告)号：US20080301371A1

公开(公告)日：2008-12-04

申请号：US11570303

申请日：2005-05-31

申请人： Itay Peled ,  Moshe Anschel ,  Yacov Efrat ,  Alon Eldar

发明人： Itay Peled ,  Moshe Anschel ,  Yacov Efrat ,  Alon Eldar

IPC分类号： G06F12/08

CPC分类号： G06F12/0804 ,  G06F12/0842 ,  G06F12/0891

摘要： A memory cache control arrangement for performing a coherency operation on a memory cache comprises a receive processor for receiving an address group indication for an address group comprising a plurality of addresses associated with a main memory. The address group indication may indicate a task identity and an address range corresponding to a memory block of the main memory. A control unit processes each line of a group of cache lines sequentially. Specifically it is determined if each cache line is associated with an address of the address group by evaluating a match criterion. If the match criterion is met, a coherency operation is performed on the cache line. If a conflict exists between the coherency operation and another memory operation the coherency means inhibits the coherency operation. The invention allows a reduced duration of a cache coherency operation. The duration is further independent of the size of the main memory address space covered by the coherency operation.

摘要翻译： 一种用于在存储器高速缓存中执行一致性操作的存储器高速缓存控制装置，包括接收处理器，用于接收包括与主存储器相关联的多个地址的地址组的地址组指示。 地址组指示可以指示对应于主存储器的存储块的任务标识和地址范围。 控制单元依次处理一组高速缓存行的每一行。 具体地说，通过评估匹配标准来确定每个高速缓存行是否与地址组的地址相关联。 如果满足匹配条件，则在高速缓存行上执行一致性操作。 如果在一致性操作和另一个存储器操作之间存在冲突，则相关性意味着禁止一致性操作。 本发明允许缓存一致性操作的持续时间缩短。 持续时间进一步与由一致性操作覆盖的主存储器地址空间的大小无关。

公开(公告)号：US20070266199A1

公开(公告)日：2007-11-15

申请号：US11574864

申请日：2004-09-07

申请人： Itay Peled ,  Moshe Anschel ,  Moshe Bachar ,  Jacob Efrat ,  Alon Eldar ,  Yakov Tokar

发明人： Itay Peled ,  Moshe Anschel ,  Moshe Bachar ,  Jacob Efrat ,  Alon Eldar ,  Yakov Tokar

IPC分类号： G06F12/00

CPC分类号： G06F12/0842

摘要： A virtual address cache comprising a comparator arranged to receive a virtual address for addressing data associated with a task and a memory, wherein the comparator is arranged to make a determination as to whether data associated with the received virtual address is stored in the memory based upon an indication that the virtual address is associated with data shared between a first task and a second task and a comparison of the received virtual address with an address associated with data stored in memory.

摘要翻译： 一种虚拟地址缓存，包括比较器，被配置为接收用于寻址与任务和存储器相关联的数据的虚拟地址，其中所述比较器被设置为基于与所接收到的虚拟地址相关联的数据是否基于 指示虚拟地址与第一任务和第二任务之间共享的数据相关联，以及所接收的虚拟地址与与存储在存储器中的数据相关联的地址的比较。

公开(公告)号：US07865691B2

公开(公告)日：2011-01-04

申请号：US11574474

申请日：2004-08-31

申请人： Itay Peled ,  Moshe Anschel ,  Moshe Bachar ,  Jacob Efrat ,  Alon Eldar ,  Yakov Tokar

发明人： Itay Peled ,  Moshe Anschel ,  Moshe Bachar ,  Jacob Efrat ,  Alon Eldar ,  Yakov Tokar

IPC分类号： G06F12/08

CPC分类号： G06F12/1063 ,  G06F12/0842

摘要： A virtual address cache and a method for sharing data. The virtual address cache includes: a memory, adapted to store virtual addresses, task identifiers and data associated with the virtual addresses and the task identifiers; and a comparator, connected to the memory, adapted to determine that data associated with a received virtual address and a received task identifier is stored in the memory if at least a portion of the received virtual address equals at least a corresponding portion of a certain stored virtual address and a stored task identifier associated with the certain stored virtual address indicates that the data is shared between multiple tasks. The method includes: receiving a virtual address and a task identifier for addressing data; determining as to whether the data is stored in a memory based upon a comparison of at least a portion of the received virtual address with at least a portion of an address associated with data stored in memory and based upon a fulfillment of the following criterion: a stored task identifier associated with the certain stored virtual address indicates that the data is shared between multiple tasks.

摘要翻译： 虚拟地址缓存和共享数据的方法。 虚拟地址缓存包括：适于存储虚拟地址，任务标识符和与虚拟地址和任务标识符相关联的数据的存储器; 以及连接到所述存储器的比较器，适于确定与所接收的虚拟地址相关联的数据和所接收的任务标识符被存储在所述存储器中，如果所接收的虚拟地址的至少一部分等于至少一个所存储的虚拟地址的对应部分 虚拟地址和与特定存储的虚拟地址相关联的存储的任务标识指示数据在多个任务之间共享。 该方法包括：接收虚拟地址和用于寻址数据的任务标识符; 基于所接收的虚拟地址的至少一部分与存储在存储器中的数据相关联的地址的至少一部分，并且基于以下标准的实现来确定数据是否存储在存储器中：a 与特定存储的虚拟地址相关联的存储的任务标识指示数据在多个任务之间共享。