公开(公告)号：US09786652B2

公开(公告)日：2017-10-10

申请号：US14854366

申请日：2015-09-15

申请人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

发明人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

IPC分类号： H01L29/74 ,  H01L29/747 ,  H01L29/00 ,  H01L21/331 ,  H01L27/082 ,  H01L29/73 ,  H01L27/02 ,  H01L29/66 ,  H01L23/60 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L27/0259 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/082 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/73 ,  H01L29/7317 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device.

公开(公告)号：US20130279051A1

公开(公告)日：2013-10-24

申请号：US13451312

申请日：2012-04-19

申请人： Chai Ean Gill ,  Rouying Zhan

发明人： Chai Ean Gill ,  Rouying Zhan

IPC分类号： H02H9/04

CPC分类号： H01L27/0259 ,  H02H9/041

摘要： An area-efficient, high voltage, dual polarity ESD protection device (200) is provided for protecting multiple pins (30, 40) against ESD events by using a plurality of stacked NPN devices (38, 48, 39) which have separately controllable breakdown voltages and which share one or common NPN devices (39), thereby reducing the footprint of the high voltage ESD protection circuits without reducing robustness and functionality.

摘要翻译： 提供了一种区域高效，高电压，双极性ESD保护装置（200），用于通过使用多个堆叠的NPN装置（38,48,39）来保护多个针脚（30,40）免受ESD事件的影响，这些NPN装置具有分别可控的击穿 电压并且共享一个或公共NPN器件（39），从而减少高压ESD保护电路的覆盖，而不降低鲁棒性和功能性。

公开(公告)号：US08279566B2

公开(公告)日：2012-10-02

申请号：US12112209

申请日：2008-04-30

申请人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

发明人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

IPC分类号： H02H9/00

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) clamp (41, 51, 61, 71, 81, 91), coupled across input-output (I/O) (22) and common (GND) (23) terminals of a protected semiconductor SC device or IC (24), comprises, an ESD transistor (ESDT) (25) with source-drain (26, 27) coupled between the GND (23) and I/O (22), a first resistor (30) coupled between gate (28) and source (26) and a second resistor (30) coupled between ESDT body (29) and source (26). Paralleling the resistors (30, 32) are control transistors (35, 35′) with gates (38, 38′) coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC (24) is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events. Parasitic leakage through the ESDT (25) during normal operation is much reduced.

摘要翻译： 被保护半导体SC器件的输入输出（I / O）（22）和公共（GND）（23）端子耦合的静电放电（ESD）钳位（41,41,61,71,81,91） IC（24）包括耦合在GND（23）和I / O（22）之间的源极 - 漏极（26,27）的ESD晶体管（ESDT）（25），耦合在栅极 28）和源极（26）以及耦合在ESDT体（29）和源极（26）之间的第二电阻器（30）。 并联电阻器（30,32）是与一个或多个偏置电源Vb，Vb'耦合的门（38,38'）的控制晶体管（35,35'）。 设备或IC（24）的主电源轨（Vdd）是Vb，Vb'的方便源。 当Vdd在装运，处理，设备组装等时关闭时，ESD触发电压Vt1为低，从而在ESD风险高时提供最大的ESD保护。 当Vdd通电时，Vt1上升到足够大的值，以避免与正常电路操作的干扰，但仍然保护ESD事件。 在正常运行期间通过ESDT（25）的寄生泄漏大大减少。

公开(公告)号：US20120119331A1

公开(公告)日：2012-05-17

申请号：US12944931

申请日：2010-11-12

申请人： Amaury Gendron ,  Chai Ean Gill ,  Vadim A. Kushner ,  Rouying Zhan

发明人： Amaury Gendron ,  Chai Ean Gill ,  Vadim A. Kushner ,  Rouying Zhan

IPC分类号： H01L29/72 ,  H01L21/331

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.

摘要翻译： 提供一种区域高效，高电压，单极性的ESD保护装置（300），其包括p型衬底（303）; 第一p阱（308-1），其形成在所述衬底中并且尺寸设置成包含连接到阴极端子的n +和p +接触区域（310,312）; 形成在所述基板中并且尺寸仅包含连接到阳极端子的p +接触区域（311）的第二独立p阱（308-2） 以及形成在基板中以围绕和分离第一和第二半导体区域的电浮置n型隔离结构（304,306,307-2）。 当超过触发电压电平的正电压被施加到阴极和阳极端子时，ESD保护装置将固有的可控硅触发到快速恢复模式，以提供通过用于放电ESD电流的结构的低阻抗路径。

公开(公告)号：US20110175198A1

公开(公告)日：2011-07-21

申请号：US12956686

申请日：2010-11-30

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L21/8228 ,  H01L27/0259 ,  H01L29/66234

摘要： A stackable electrostatic discharge (ESD) protection clamp (21) for protecting a circuit core (24) comprises, a bipolar transistor (56, 58) having a base region (74, 51, 52, 85) with a base contact (77) therein and an emitter (78) spaced a lateral distance Lbe from the base contact (77), and a collector (80, 86, 762) proximate the base region (74, 51, 52, 85). The base region (74, 51, 52, 85) comprises a first portion (51) including the base contact (77) and emitter (78), and a second portion (52) with a lateral boundary (752) separated from the collector (86, 762) by a breakdown region (84) whose width D controls the clamp trigger voltage, the second portion (52) lying between the first portion (51) and the boundary (752). The damage-onset threshold current It2 of the ESD clamp (21) is improved by increasing the parasitic resistance Rbe of the emitter-base region (74, 51, 52, 85), by for example, increasing Lbe or decreasing the relative doping density of the first portion (51) or a combination thereof.

摘要翻译： 用于保护电路芯（24）的可堆叠静电放电（ESD）保护夹具（21）包括：具有基部接触（77）的基极区域（74,51,52,85）的双极晶体管（56,58） 以及与基部触点（77）间隔开横向距离Lbe的发射器（78）和靠近基部区域（74,51,52,85）的收集器（80,86,762）。 基部区域（74,51,52,85）包括包括基部触头（77）和发射极（78）的第一部分（51）和具有与集电器分离的侧边界（752）的第二部分（52） （86,762）由其宽度D控制钳位触发电压的击穿区域（84），第二部分（52）位于第一部分（51）和边界（752）之间。 通过增加发射极 - 基极区（74,51,52,85）的寄生电阻Rbe，例如增加Lbe或减小相对掺杂密度来改善ESD钳位（21）的损伤起始阈值电流It2 的第一部分（51）或其组合。

公开(公告)号：US09177952B2

公开(公告)日：2015-11-03

申请号：US14053716

申请日：2013-10-15

申请人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

发明人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

IPC分类号： H01L29/74 ,  H01L29/747 ,  H01L29/00 ,  H01L21/331 ,  H01L27/082 ,  H01L29/73 ,  H01L27/02 ,  H01L29/66 ,  H01L23/60

CPC分类号： H01L27/0259 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/082 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/73 ,  H01L29/7317 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) protection device includes a semiconductor substrate comprising a buried insulator layer and a semiconductor layer over the buried insulator layer having a first conductivity type, and first and second bipolar transistor devices disposed in the semiconductor layer, laterally spaced from one another, and sharing a common collector region having a second conductivity type. The first and second bipolar transistor devices are configured in an asymmetrical arrangement in which the second bipolar transistor device includes a buried doped layer having the second conductivity type and extending along the buried insulator layer from the common collector region across a device area of the second bipolar transistor device.

摘要翻译： 静电放电（ESD）保护装置包括半导体衬底，该半导体衬底包括掩埋绝缘体层和在具有第一导电类型的掩埋绝缘体层上的半导体层，以及设置在半导体层中的彼此横向间隔开的第一和第二双极晶体管器件 并且共享具有第二导电类型的公共收集器区域。 第一和第二双极晶体管器件被配置成非对称布置，其中第二双极晶体管器件包括具有第二导电类型的掩埋掺杂层，并且沿着埋在绝缘体层的跨第二极二极管的器件区域的公共集电极区域延伸 晶体管器件。

公开(公告)号：US08432654B2

公开(公告)日：2013-04-30

申请号：US13612466

申请日：2012-09-12

申请人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

发明人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

IPC分类号： H02H9/00

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) clamp, coupled across input-output (I/O) and common (GND) terminals of a protected semiconductor device or integrated circuit is provided. One ESD clamp comprises an ESD transistor (ESDT) with source-drain coupled between the GND and I/O terminals, a first resistor coupled between the gate and source and a second resistor coupled between the ESDT body and source. Paralleling the resistors are control transistors with gates coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

摘要翻译： 提供了耦合在受保护的半导体器件或集成电路的输入输出（I / O）和公共（GND）端子之间的静电放电（ESD）钳位。 一个ESD钳位包括源极 - 漏极耦合在GND和I / O端子之间的ESD晶体管（ESDT），耦合在栅极和源极之间的第一个电阻器和耦合在ESDT体和源极之间的第二个电阻器。 并联电阻器是控制晶体管，其栅极耦合到一个或多个偏置电源Vb，Vb'。 设备或IC的主电源轨（Vdd）是Vb，Vb'的方便源。 当Vdd在装运，处理，设备组装等时关闭时，ESD触发电压Vt1为低，从而在ESD风险高时提供最大的ESD保护。 当Vdd通电时，Vt1上升到足够大的值，以避免与正常电路操作的干扰，但仍然保护ESD事件。

公开(公告)号：US08390092B2

公开(公告)日：2013-03-05

申请号：US12944931

申请日：2010-11-12

申请人： Amaury Gendron ,  Chai Ean Gill ,  Vadim A. Kushner ,  Rouying Zhan

发明人： Amaury Gendron ,  Chai Ean Gill ,  Vadim A. Kushner ,  Rouying Zhan

IPC分类号： H01L23/58

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.

公开(公告)号：US20120231587A1

公开(公告)日：2012-09-13

申请号：US13480924

申请日：2012-05-25

申请人： AMAURY GENDRON ,  Chai Ean Gill ,  Rouying Zhan

发明人： AMAURY GENDRON ,  Chai Ean Gill ,  Rouying Zhan

IPC分类号： H01L21/33

CPC分类号： H01L21/00 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/66121 ,  H01L29/87

摘要： Embodiments include methods for forming an electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, where the ESD protection device includes first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first and second widths. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.

摘要翻译： 实施例包括用于形成耦合在输入输出（I / O）和核心电路的公共端子之间的静电放电（ESD）保护装置的方法，其中ESD保护装置包括第一和第二合并双极晶体管。 第一晶体管的基极用作第二晶体管的集电极，第二晶体管的基极用作第一晶体管的集电极，基极分别具有第一和第二宽度。 第一电阻耦合在第一晶体管的发射极和基极之间，第二电阻耦合在第二晶体管的发射极和基极之间。 ESD触发电压Vt1和保持电压Vh可以通过选择合适的基极宽度和电阻来独立优化。 通过将Vh增加到大致相等的Vt1，ESD保护更稳健，特别是对于具有窄设计窗口的应用，例如，工作电压接近劣化电压。

公开(公告)号：US09659922B2

公开(公告)日：2017-05-23

申请号：US13917580

申请日：2013-06-13

申请人： Rouying Zhan ,  Chai Ean Gill

发明人： Rouying Zhan ,  Chai Ean Gill

IPC分类号： H01L27/02

CPC分类号： H01L27/0262 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66234 ,  H02H9/046

摘要： An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer.