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    Circuit arrangement for capacitive read signal amplification in an integrated semiconductor store with storage cells in MTL technology
    1.
    发明授权
    Circuit arrangement for capacitive read signal amplification in an integrated semiconductor store with storage cells in MTL technology 失效
    集成半导体存储器中电容式读取信号放大的电路布置与MTL技术中的存储单元

    公开(公告)号：US4397002A

    公开(公告)日：1983-08-02

    申请号：US179581

    申请日：1980-08-21

    申请人： Rudolf Brosch ,  Helmut H. Heimeier ,  Wilfried Klein ,  Friedrich Wernicke

    发明人： Rudolf Brosch ,  Helmut H. Heimeier ,  Wilfried Klein ,  Friedrich Wernicke

    IPC分类号： G11C11/41 ,  G11C11/411 ,  G11C11/416 ,  G11C7/00

    CPC分类号： G11C11/4113

    摘要： After a controlled strong lowering of the word line potential for the purpose of addressing a cell, said potential is immediately recharged simultaneously increasing the potential on the N side of the two PNP injectors of the cell and causing the injector capacitances of the selected storage cells and the bit line capacitances to form a capacitive voltage divider, so that the bit lines connected thereto are recharged to different degrees by the different magnitudes of the injector capacitances. Thus, the differential signal formed on the bit lines is noticeably amplified by the supply of currents of different magnitudes.

    摘要翻译： 在用于寻址单元的目的电位的受控强降低之后，所述电位立即再充电，同时增加电池的两个PNP注入器的N侧上的电位，并导致所选择的存储单元的注入器电容和 位线电容以形成电容分压器，使得连接到其上的位线被不同程度地通过注射器电容的不同大小进行再充电。 因此，通过不同幅度的电流的供给，在位线上形成的差分信号被显着地放大。

    Integrated semiconductor memory and method of operating same
    2.
    发明授权
    Integrated semiconductor memory and method of operating same 失效
    集成半导体存储器及其操作方法

    公开(公告)号：US4313179A

    公开(公告)日：1982-01-26

    申请号：US133383

    申请日：1980-03-24

    申请人： Helmut H. Heimeier ,  Wilfried Klein ,  Knut Najmann ,  Friedrich C. Wernicke

    发明人： Helmut H. Heimeier ,  Wilfried Klein ,  Knut Najmann ,  Friedrich C. Wernicke

    IPC分类号： G11C11/41 ,  G11C7/02 ,  G11C7/06 ,  G11C7/20 ,  G11C11/4091 ,  G11C11/416 ,  G11C7/00

    CPC分类号： G11C7/062 ,  G11C11/4091 ,  G11C11/416 ,  G11C7/065 ,  G11C7/20

    摘要： An integrated semiconductor memory having memory cells which have (or are designed to have) inherent asymmetrical access times for the distinguishable memory states thereof. The memory is operated on the basis of the shorter access time. This is accomplished by utilizing an oppositely asymmetrical sense system, preferably in the form of a pre-set sense latch.For example, in the case of a digital memory with the reading of a "0" state having a shorter access time than the reading of a "1" state, at the beginning of a read operation a sense latch is set to the (slower) "1" state. Thus, only in the case of reading a "0" is the state of the latch changed to the "0" state. Thus, the actual access time is no longer determined by the longer access time, namely, the reading of a "1". The access time is determined by the shorter access time, namely, the reading of a "0".The concept may also be used if the sense latch has an asymmetric access time. Then it is advantageous to intentionally choose a corresponding asymetrical memory cell design.

    摘要翻译： 具有存储单元的集成半导体存储器，其具有（或被设计为具有）用于其可分辨存储器状态的固有不对称访问时间。 存储器在更短的访问时间的基础上运行。 这通过利用相对不对称的感测系统来实现，优选地以预设的感测锁存器的形式。 例如，在具有比读取“1”状态的访问时间短的读取“0”状态的数字存储器的情况下，在读操作开始时，将感测锁存器设置为（较慢 ）“1”状态。 因此，只有在读取“0”的情况下，锁存器的状态变为“0”状态。 因此，实际的访问时间不再由更长的访问时间，即读取“1”确定。 访问时间由更短的访问时间确定，即读取“0”。 如果感测锁存器具有不对称访问时间，则也可以使用该概念。 那么有意的是选择相应的非对称存储单元设计。