公开(公告)号：US20070072571A1

公开(公告)日：2007-03-29

申请号：US11341184

申请日：2006-01-28

申请人： Runhua Sun ,  Christian Holenstein ,  James Jaffee

发明人： Runhua Sun ,  Christian Holenstein ,  James Jaffee

IPC分类号： H04B1/18 ,  H04B1/16

CPC分类号： H03D3/008

摘要： Techniques for cancelling DC offset are described. A DC offset cancellation circuit in a receiver cancels DC offsets caused by leaked LO (local oscillator) signals from a LO signal generator. The receiver first calibrates itself by using the DC offset cancellation circuit during a transmit mode. During the calibration, the DC offset cancellation circuit stores the DC offset voltage signal caused by the leaked LO signals. During a receiving mode when the receiver is receiving a signal, the receiver subtracts the stored DC offset voltage signal from the received signal to cancel the DC offsets caused by leaked LO signals.

摘要翻译： 描述了消除DC偏移的技术。 接收器中的DC偏移消除电路消除由LO信号发生器泄漏的LO（本地振荡器）信号引起的DC偏移。 接收机首先通过在发送模式期间使用DC偏移消除电路进行自校准。 在校准期间，DC偏移消除电路存储由泄露的LO信号引起的DC偏移电压信号。 在接收器接收信号的接收模式期间，接收机从接收信号中减去存储的直流失调电压信号，以消除由泄露的LO信号引起的直流偏移。

公开(公告)号：US06476675B1

公开(公告)日：2002-11-05

申请号：US09747470

申请日：2000-12-20

申请人： Runhua Sun

发明人： Runhua Sun

IPC分类号： H03F345

CPC分类号： H03F3/45188 ,  H03F2203/45526 ,  H03F2203/45631 ,  H03F2203/45651 ,  H03F2203/45652

摘要： A two-stage op-amp circuit including a double-cascode telescopic op-amp circuit in the input stage and a fully-differential op-amp circuit in the output stage and having very high open-loop DC gain, very high unity-gain frequency, and relatively very low power consumption is presented. The input stage op-amp circuit and the output stage op-amp circuit are each comprised of a plurality of electrically connected MOSFET's. The input stage op-amp circuit provides very high gain, high input resistance, and large common mode rejection. The output stage op-amp circuit provides gain, low output resistance, and minimal output loss.

摘要翻译： 一个两级运算放大器电路，包括输入级中的双共源共模放大运算放大器电路和输出级中的全差分运算放大器电路，具有非常高的开环直流增益，非常高的单位增益 频率和相对非常低的功耗。 输入级运算放大器电路和输出级运算放大器电路各自由多个电连接的MOSFET组成。 输入级运算放大器电路提供非常高的增益，高输入电阻和大的共模抑制。 输出级运算放大器电路提供增益，低输出电阻和最小的输出损耗。

公开(公告)号：US06664853B1

公开(公告)日：2003-12-16

申请号：US10061735

申请日：2002-01-31

申请人： Runhua Sun ,  Thomas Clark Bryan ,  Zhixiang Jason Liu

发明人： Runhua Sun ,  Thomas Clark Bryan ,  Zhixiang Jason Liu

IPC分类号： H03F345

CPC分类号： H03F3/45197 ,  H03F2203/45458 ,  H03F2203/45496 ,  H03F2203/45631 ,  H03F2203/45702

摘要： An impedance element connecting the outputs of two transistors of a wide-bandwidth amplifier forms a zero. The output of transistor is connected to a current source. The wide-bandwidth amplifier has a bandwidth greater than conventional amplifiers utilizing a single current source without an increase in power dissipation.

摘要翻译： 连接宽带宽放大器的两个晶体管的输出的阻抗元件形成零。 晶体管的输出端连接到电流源。 宽带宽放大器的带宽大于传统放大器，而不会增加功耗。

公开(公告)号：US06353361B1

公开(公告)日：2002-03-05

申请号：US09746756

申请日：2000-12-20

申请人： Runhua Sun

发明人： Runhua Sun

IPC分类号： H03F345

CPC分类号： H03F3/45188 ,  H03F3/45183 ,  H03F2200/153 ,  H03F2203/45631 ,  H03F2203/45651 ,  H03F2203/45652

摘要： A differential, two-stage op-amp circuit comprised of a plurality of electrically connected MOSFET's and including a telescopic op-amp circuit integrated with gain-boost amplifier circuits in the input stage and a fully-differential op-amp circuit in the output stage and having very high open-loop DC gain, very high unity-gain frequency, and considerably low power consumption is presented. The gain-boost amplifiers are configured as fully-differential op-amps, one being configured to be electrically connected to PMOS FET circuitry and the other being configured to be electrically connected to NMOS FET circuitry. The input stage op-amp circuit provides high gain, high input resistance, and large common mode rejection. The gain-boost op-amp circuits and the input stage form a local unity-gain feedback, and the outputs of the gain-boost op-amp circuits are adaptively stabilized. The output stage op-amp circuit provides gain, low output resistance, and minimal output loss.

摘要翻译： 差分两级运算放大器电路由多个电气连接的MOSFET组成，包括与输入级中的增益 - 升压放大器电路集成的伸缩运算放大器电路和输出级中的全差分运算放大器电路 并且具有非常高的开环DC增益，非常高的单位增益频率和相当低的功耗。 增益 - 升压放大器被配置为全差分运算放大器，一个被配置为电连接到PMOS FET电路，另一个被配置为电连接到NMOS FET电路。 输入级运算放大器电路提供高增益，高输入电阻和大型共模抑制。 增益升压运算放大器电路和输入级形成局部单位增益反馈，并且增益 - 升压运算放大器电路的输出自适应地稳定。 输出级运算放大器电路提供增益，低输出电阻和最小的输出损耗。

公开(公告)号：US06825730B1

公开(公告)日：2004-11-30

申请号：US10403606

申请日：2003-03-31

申请人： Runhua Sun

发明人： Runhua Sun

IPC分类号： H03L700

CPC分类号： H03L7/0898 ,  H03L7/0896

摘要： A charge-pump and a method are provided for conditioning the phase detector output in a phase-locked loop (PLL). The method comprises: accepting a pair of differential phase detector (PD) output signals (up/upb and dn/dnb); connecting each pair of differential PD outputs to first and second charge-pump differential sections; supplying differential charge-pump outputs (Vout+/Vout−) in response to the pair of differential PD output signals; and, disconnecting the charge-pump differential section outputs from the loop filter inputs when the PD differential outputs (up/dn and upb/dnb) are equal. In some aspects, supplying differential charge-pump outputs (Vout+/Vout−) in response to the pair of differential PD output signals includes sourcing a first current through the first charge-pump differential section and sourcing a second current through the second charge-pump differential section. Then, the method further comprises maintaining the first current equal to the second current.

摘要翻译： 提供电荷泵和方法来调节锁相环（PLL）中的相位检测器输出。 该方法包括：接收一对差分相位检测器（PD）输出信号（up / upb和dn / dnb）; 将每对差分PD输出连接到第一和第二电荷泵差动部分; 响应一对差分PD输出信号，提供差分电荷泵输出（Vout + / Vout-）; 并且当PD差分输出（up / dn和upb / dnb）相等时，断开来自环路滤波器输入的电荷泵差分部分输出。 在一些方面，响应于一对差分PD输出信号供应差分电荷泵输出（Vout + / Vout-）包括通过第一电荷泵差分部分提供第一电流并且通过第二电荷泵 差分段。 然后，该方法还包括保持第一电流等于第二电流。

公开(公告)号：US06538512B2

公开(公告)日：2003-03-25

申请号：US10198848

申请日：2002-07-18

申请人： Runhua Sun

发明人： Runhua Sun

IPC分类号： H03F345

CPC分类号： H03F3/45188 ,  H03F2203/45526 ,  H03F2203/45631 ,  H03F2203/45651 ,  H03F2203/45652

摘要： A two-stage op-amp circuit including a double-cascode telescopic op-amp circuit in the input stage and a fully-differential op-amp circuit in the output stage and having very high open-loop DC gain, very high unity-gain frequency, and relatively very low power consumption is presented. The input stage op-amp circuit and the output stage op-amp circuit are each comprised of a plurality of electrically connected MOSFET's. The input stage op-amp circuit provides very high gain, high input resistance, and large common mode rejection. The output stage op-amp circuit provides gain, low output resistance, and minimal output loss.