公开(公告)号：US20080208562A1

公开(公告)日：2008-08-28

申请号：US12148205

申请日：2008-04-17

申请人： Russell W. Guenthner ,  Sidney L. Andress ,  John Heath

发明人： Russell W. Guenthner ,  Sidney L. Andress ,  John Heath

IPC分类号： G06F9/455

CPC分类号： G06F9/30043 ,  G06F9/30101 ,  G06F9/30174

摘要： Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a “containing” word stored in the memory of the host machine. A “LOAD64” instruction loads the emulator memory location representing an emulated “Q” (supplementary accumulator) register with the “normal” 36-bits of the containing word. At the same time, the “upper” 28 bits of the 64-bit containing word is copied into the emulator memory location representing an emulated “A” (accumulator) register. Thus, the emulated 36-bit machine “sees” and can examine the 64-bit word in its entirety. A “Store64” instruction stores the emulated “Q” register contents into the lower 36-bits of the 64-bit containing word, and at the same time stores the lower 28 bits of the emulated “A” register contents into the upper 28 bits of the 64-bit containing word.

摘要翻译： 提供了用于在主机64位机器上仿真的目标36位机器的指令集的两个唯一指令，以便实现模拟应用程序对存储在存储器中的“包含”字的可见性 主机。 “LOAD64”指令将模拟器存储位置加载到包含字的“正常”36位的模拟“Q”（补充累加器）寄存器中。 同时，64位包含字的“上”28位被复制到表示仿真“A”（累加器）寄存器的仿真器存储单元中。 因此，仿真的36位机器“看到”并且可以检查64位字的整体。 “Store64”指令将模拟的“Q”寄存器内容存储到64位包含字的低36位，同时将模拟的“A”寄存器内容的低28位存储到高位28位 的64位包含字。

公开(公告)号：US07689403B2

公开(公告)日：2010-03-30

申请号：US12148205

申请日：2008-04-17

申请人： Russell W. Guenthner ,  Sidney L Andress ,  John Heath

发明人： Russell W. Guenthner ,  Sidney L Andress ,  John Heath

IPC分类号： G06F9/455

CPC分类号： G06F9/30043 ,  G06F9/30101 ,  G06F9/30174

摘要： Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a “containing” word stored in the memory of the host machine. A “LOAD64” instruction loads the emulator memory location representing an emulated “Q” (supplementary accumulator) register with the “normal” 36-bits of the containing word. At the same time, the “upper” 28 bits of the 64-bit containing word is copied into the emulator memory location representing an emulated “A” (accumulator) register. Thus, the emulated 36-bit machine “sees” and can examine the 64-bit word in its entirety. A “Store64” instruction stores the emulated “Q” register contents into the lower 36-bits of the 64-bit containing word, and at the same time stores the lower 28 bits of the emulated “A” register contents into the upper 28 bits of the 64-bit containing word.

摘要翻译： 提供了用于在主机64位机器上仿真的目标36位机器的指令集的两个唯一指令，以便实现模拟应用程序对存储在存储器中的“包含”字的可见性 主机。 “LOAD64”指令将模拟器存储位置加载到包含字的“正常”36位的模拟“Q”（补充累加器）寄存器中。 同时，64位包含字的“上”28位被复制到表示仿真“A”（累加器）寄存器的仿真器存储单元中。 因此，仿真的36位机器“看到”并且可以检查64位字的整体。 “Store64”指令将模拟的“Q”寄存器内容存储到64位包含字的低36位，同时将模拟的“A”寄存器内容的低28位存储到高位28位 的64位包含字。

公开(公告)号：US07406406B2

公开(公告)日：2008-07-29

申请号：US11006414

申请日：2004-12-07

申请人： Russell W. Guenthner ,  Sidney L. Andress ,  John E. Heath

发明人： Russell W. Guenthner ,  Sidney L. Andress ,  John E. Heath

IPC分类号： G06F9/44 ,  G06F9/455 ,  G06F12/00

CPC分类号： G06F9/30043 ,  G06F9/30101 ,  G06F9/30174

摘要： Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a “containing” word stored in the memory of the host machine. A “LOAD64” instruction loads the emulator memory location representing an emulated “Q” (supplementary accumulator) register with the “normal” 36-bits of the containing word. At the same time, the “upper” 28 bits of the 64-bit containing word is copied into the emulator memory location representing an emulated “A” (accumulator) register. Thus, the emulated 36-bit machine “sees” and can examine the 64-bit word in its entirety. A “Store64” instruction stores the emulated “Q” register contents into the lower 36-bits of the 64-bit containing word, and at the same time stores the lower 28 bits of the emulated “A” register contents into the upper 28 bits of the 64-bit containing word.

摘要翻译： 提供了用于在主机64位机器上仿真的目标36位机器的指令集的两个唯一指令，以便实现模拟应用程序对存储在存储器中的“包含”字的可见性 主机。 “LOAD64”指令将模拟器存储位置加载到包含字的“正常”36位的模拟“Q”（补充累加器）寄存器中。 同时，64位包含字的“上”28位被复制到表示仿真“A”（累加器）寄存器的仿真器存储单元中。 因此，仿真的36位机器“看到”并且可以检查64位字的整体。 “Store64”指令将模拟的“Q”寄存器内容存储到64位包含字的低36位，同时将仿真的“A”寄存器内容的低28位存储到高位28位 的64位包含字。

公开(公告)号：US08869126B2

公开(公告)日：2014-10-21

申请号：US13729490

申请日：2012-12-28

申请人： Cynthia S. Guenthner ,  Russell W. Guenthner ,  John Edward Heath ,  Albert Henry John Wigchert ,  F. Michel Brown ,  Nicholas John Colasacco ,  Clinton B. Eckard

发明人： Cynthia S. Guenthner ,  Russell W. Guenthner ,  John Edward Heath ,  Albert Henry John Wigchert ,  F. Michel Brown ,  Nicholas John Colasacco ,  Clinton B. Eckard

IPC分类号： G06F9/45

CPC分类号： G06F8/456

摘要： A method and apparatus is disclosed for compilation of an original Cobol program with support for improved performance by increased parallelism during execution using multiple threads of processing. The approach includes a two stage compilation process, the first compilation/translation step by a first specialized compiler/translator that takes as input a Cobol source program that includes parallelization directives, and produces as output an intermediate computer program in a second computer programming language, the intermediate program including parallelization directives in the second computer programming language. The intermediate program is then compiled utilizing a selected second compiler that provides support for parallelism described in the second programming language. The approach optionally allows for use of pragmas serving as parallelization directives to the compiler in the original Cobol program or in the intermediate program.

摘要翻译： 公开了一种用于编译原始Cobol程序的方法和装置，其支持通过使用多个处理线程在执行期间通过增加的并行性来提高性能。 该方法包括两阶段编译过程，第一个专业编译器/翻译器的第一个编译/翻译步骤，将包含并行化指令的Cobol源程序作为输入，并以第二计算机编程语言生成中间计算机程序作为输出， 中间程序包括第二计算机编程语言中的并行化指令。 然后使用提供对第二编程语言中描述的并行性的支持的所选择的第二编译器来编译中间程序。 该方法可以允许在原始Cobol程序或中间程序中使用用作并行指令的编译指示给编译器。

公开(公告)号：US08856759B2

公开(公告)日：2014-10-07

申请号：US12658017

申请日：2010-02-01

申请人： Russell W. Guenthner ,  Clinton B. Eckard

发明人： Russell W. Guenthner ,  Clinton B. Eckard

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F8/49 ,  G06F8/41 ,  G06F8/4441 ,  G06F9/4484

摘要： A method and apparatus is disclosed providing an improvement in performance for arithmetic computations by a computer system for calculations which include decimal numeric variables. The improvement in at least one embodiment includes use of a special compiler in cooperation with a special decimal numeric subroutine library. The compiler provides comparative alignment information based upon comparing alignments of a plurality of decimal variables. The decimal subroutine library can then provide improved performance at run time by utilizing the information compared by the compiler at compiler time rather than making those computations repeatedly at run time.

摘要翻译： 公开了一种方法和装置，其通过计算机系统提供包括十进制数字变量的计算的算术计算性能的改进。 至少一个实施例的改进包括与特殊的十进制数字子程序库协同使用特殊的编译器。 编译器基于比较多个十进制变量的比对来提供比较对齐信息。 然后，十进制子程序库可以通过利用编译器在编译器时比较的信息在运行时提供改进的性能，而不是在运行时重复进行这些计算。

公开(公告)号：US20110191755A1

公开(公告)日：2011-08-04

申请号：US12658017

申请日：2010-02-01

申请人： Russell W. Guenthner ,  Clinton B. Eckard

发明人： Russell W. Guenthner ,  Clinton B. Eckard

IPC分类号： G06F9/45

CPC分类号： G06F8/49 ,  G06F8/41 ,  G06F8/4441 ,  G06F9/4484

摘要： A method and apparatus is disclosed providing an improvement in performance for arithmetic computations by a computer system for calculations which include decimal numeric variables. The improvement in at least one embodiment includes use of a special compiler in cooperation with a special decimal numeric subroutine library. The compiler provides comparative alignment information based upon comparing alignments of a plurality of decimal variables. The decimal subroutine library can then provide improved performance at run time by utilizing the information compared by the compiler at compiler time rather than making those computations repeatedly at run time.

摘要翻译： 公开了一种方法和装置，其通过计算机系统提供包括十进制数字变量的计算的算术计算性能的改进。 至少一个实施例的改进包括与特殊的十进制数字子程序库协同使用特殊的编译器。 编译器基于比较多个十进制变量的比对来提供比较对齐信息。 然后，十进制子程序库可以通过利用编译器在编译器时比较的信息在运行时提供改进的性能，而不是在运行时重复进行这些计算。

公开(公告)号：US5435000A

公开(公告)日：1995-07-18

申请号：US65105

申请日：1993-05-19

申请人： Donald C. Boothroyd ,  Mark T. Chase ,  Russell W. Guenthner

发明人： Donald C. Boothroyd ,  Mark T. Chase ,  Russell W. Guenthner

IPC分类号： G06F11/16 ,  G06F12/08 ,  H04L1/22 ,  G06F17/30 ,  H04L1/00

CPC分类号： G06F11/1633 ,  G06F12/0848 ,  H04L1/22

摘要： In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information. Each cache unit includes bit-by-bit comparison circuitry to validate the half-byte results received from both BPUs in the case of single precision operations, and, in the case of double precision operation, one cache unit employs the same bit-by-bit comparison circuitry to validate, for both cache units, the result parity bits, and hence the half-byte results, received from both BPUs.

摘要翻译： 为了在包含重复的BPU的CPU中验证完整性的数据操作结果，哪些BPU通常在单个VLSI电路芯片上实现，并且能够执行单精度和双精度数据操作操作，则采用两个高速缓存单元。 每个缓存单元专用于处理半字节的信息，并且包含高度可靠的数据验证逻辑，而不需要从每个BPU提供双字宽输出总线。 通过将每个缓存单元专用于处理半字节的信息来获得降低每个VLSI芯片的引导计数的这个特征。 每个缓存单元包括逐位比较电路，用于在单精度操作的情况下验证从两个BPU接收的半字节结果，并且在双精度操作的情况下，一个高速缓存单元采用相同的逐位比较， 位比较电路，用于两个缓存单元，验证从两个BPU接收到的结果奇偶校验位，并因此验证半字节结果。

公开(公告)号：US09182962B2

公开(公告)日：2015-11-10

申请号：US13314041

申请日：2011-12-07

申请人： Todd Bradley Kneisel ,  Cynthia S. Guenthner ,  Albert Henry John Wigchert ,  Nicholas John Colasacco ,  Russell W. Guenthner ,  John Edward Heath ,  Clinton B. Eckard

发明人： Todd Bradley Kneisel ,  Cynthia S. Guenthner ,  Albert Henry John Wigchert ,  Nicholas John Colasacco ,  Russell W. Guenthner ,  John Edward Heath ,  Clinton B. Eckard

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F8/51 ,  G06F8/31

摘要： A method is disclosed for translating by a computer system of a COBOL computer program into a translated computer program in a readable and maintainable syntax in an object oriented programming language. The translated program including variable names equivalent to the original COBOL variable names and with attributes described in COBOL syntax. The translating method further providing for memory allocation in the translated computer program for storage of “COBOL” variables compatible with that of the original COBOL program; a description of program flow that is readable, and utilizing arithmetic operators to describe operations between COBOL variables. Also disclosed is a special object oriented run-time library for creating and performing operations between COBOL numeric objects, including maintaining storage of variable content in the original COBOL format, and for enabling readability of the translated source code by allowing arguments for variable type descriptions to be expressed in COBOL syntax.

摘要翻译： 公开了一种通过计算机系统将COBOL计算机程序翻译成面向对象编程语言的可读和可维护语法的翻译计算机程序的方法。 翻译的程序包括与原始COBOL变量名称等效的变量名称，并具有COBOL语法中描述的属性。 翻译方法进一步提供翻译的计算机程序中的存储器分配，用于存储与原始COBOL程序兼容的“COBOL”变量; 描述可读的程序流程，并利用算术运算符来描述COBOL变量之间的操作。 还公开了一种特殊的面向对象的运行时库，用于在COBOL数字对象之间创建和执行操作，包括保持原始COBOL格式的可变内容的存储，以及通过允许变量类型描述的参数来实现所翻译的源代码的可读性 用COBOL语法表达。

公开(公告)号：US07314491B2

公开(公告)日：2008-01-01

申请号：US11025639

申请日：2004-12-29

申请人： Russell W. Guenthner ,  Rodney B. Schultz ,  F. Michel Brown ,  Stefan R. Bohult ,  William J Brophy

发明人： Russell W. Guenthner ,  Rodney B. Schultz ,  F. Michel Brown ,  Stefan R. Bohult ,  William J Brophy

IPC分类号： G06F9/455

CPC分类号： G06F9/45537 ,  Y10S707/99936

摘要： This invention relates to the art of computer system emulation and, more particularly, to a computer system emulator in which the functions normally performed by the hardware in a legacy central processor unit are emulated by a software program. The invention is to enhance the emulated instruction set beyond that of the legacy machine such to include as new single instructions a method for invoking operating system functions, with the machine coding of the operating system functions now being performed by machine code native to the new host machine, rather than as a sequence of emulated legacy instructions.

摘要翻译： 本发明涉及计算机系统仿真技术，更具体地说，涉及一种计算机系统仿真器，其中由传统中央处理器单元中的硬件正常执行的功能由软件程序仿真。 本发明是为了增强仿真指令集超出传统机器的指令集，以便将新的单个指令作为一种用于调用操作系统功能的方法，其中操作系统功能的机器编码现在由原始的机器代码执行 机器，而不是作为仿真遗留指令的序列。

公开(公告)号：US06442676B1

公开(公告)日：2002-08-27

申请号：US09345330

申请日：1999-06-30

申请人： Russell W. Guenthner

发明人： Russell W. Guenthner

IPC分类号： G06F930

CPC分类号： G06F9/3885 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30141 ,  G06F9/30149

摘要： A data processing system contains a processor supporting both Narrow and Wide instructions and Narrow and Wide word size fixed-point and floating-point operands. The processor communicates over a bus utilizing a Wide word size with the remainder of the data processing system consisting of industry standard memory and peripheral devices. Narrow word sized instructions are stored on Wide word-sized storage devices. In a preferred embodiment, the processor bus has a first integer number of significant data lines. The processor is responsively coupled to the processor bus and includes a first decoder for decoding a first set of instructions received over the set of processor data lines, The first set of instructions each contains a second integer number, less than the first integer number, of significant bits. Fixed point arithmetic operations of a first class are performed in response to instruction decode by the first decoder on a first set of fixed point operands received over the set of processor data lines, wherein each of the first set of fixed point operands contains the second integer number of bits. Fixed point arithmetic operations of a second class are performed on a second set of fixed point operands received over the set of processor data lines, wherein each of the second set of fixed point operands contains the first integer number of bits. Corresponding processing is carried out in performing first and second classes of floating point operations.

摘要翻译： 数据处理系统包含支持窄指令和宽指令的处理器以及窄字宽和宽字大小的定点和浮点操作数。 处理器通过总线利用宽字大小进行通信，其余的数据处理系统由工业标准存储器和外围设备组成。 窄字大小的指令存储在宽字体大小的存储设备上。 在优选实施例中，处理器总线具有第一整数个有效数据线。 处理器响应地耦合到处理器总线，并且包括用于解码在该组处理器数据线上接收的第一组指令的第一解码器。第一组指令各自包含小于第一整数的第二整数 有意义的位。 响应于第一解码器对在该组处理器数据线上接收的第一组固定点操作数进行指令解码来执行第一类的定点算术运算，其中第一组固定点操作数中的每一个包含第二整数 位数。 第二类的定点算术运算是在经过一组处理器数据线接收的第二组固定点操作数上执行的，其中第二组固定点操作数中的每一个包含第一整数位。 在执行第一和第二类浮点运算时执行相应的处理。