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公开(公告)号：US5424667A
公开(公告)日：1995-06-13
申请号：US962974
申请日：1992-10-15
申请人： Ryoichi Sakai , Iwao Akiyama , Yasumasa Fujisawa
发明人： Ryoichi Sakai , Iwao Akiyama , Yasumasa Fujisawa
CPC分类号： G06F1/0328 , G06F2101/04
摘要： A DDS type variable frequency signal generator generates a jitter free and stable output signal regardless of the address interval. If the total number of addressable memory locations of a memory storing digital data is divisible without remainder by an initial address interval, then the memory is read every initial address interval with a clock signal of a predetermined frequency. If the total number of addressable memory locations is not divisible without remainder by the initial address interval, then the address interval is modified to a value that is divisible without remainder into the total number of addressable memory locations and the clock frequency is modified in accordance with this modification of the address interval. The memory is read every modified address interval with the modified clock signal.
摘要翻译： 无论地址间隔如何，DDS型可变频率信号发生器产生无抖动和稳定的输出信号。 如果存储数字数据的存储器的可寻址存储器位置的总数可被除以初始地址间隔的余数，则以每个初始地址间隔读取具有预定频率的时钟信号的存储器。 如果可寻址存储器位置的总数不能被除以初始地址间隔的余数，则地址间隔被修改为可以被除去的值，而没有余数到可寻址存储器位置的总数中，并且时钟频率根据 这个地址间隔的修改。 每个修改的地址间隔读取存储器与修改的时钟信号。
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公开(公告)号：US07284025B2
公开(公告)日：2007-10-16
申请号：US10739591
申请日：2003-12-18
IPC分类号： G06F1/02
CPC分类号： G06F1/0328
摘要： A DDS pulse generator has an accumulator that accumulates a phase increment value to produce phase accumulator values, and has a lookup table that contains a digital representation of a pulse waveform such that a pulse output signal is produced from the lookup table in response to the phase accumulator values. To change a period of the pulse output signal without changing edge positions a programmable modulo value is used. An address mapper is situated between the accumulator and address lines of the lookup table to map the rising and falling edge portions of the phase accumulator values into large regions of the lookup table, while phase accumulator values corresponding to high and low logic levels are mapped into small regions of the lookup table. The resulting pulse output signal has easily independently controlled period and pulse width as well as rising and falling edge speeds. By making better use of the lookup table it is possible to generate very narrow pulses with low repetition rates or pulses in which the rise time and fall time are very different from the period.
摘要翻译： DDS脉冲发生器具有累加相位增量值以产生相位累加器值的累加器，并且具有包含脉冲波形的数字表示的查找表，使得响应于相位从查找表产生脉冲输出信号 累加器值。 为了改变脉冲输出信号的周期而不改变边沿位置，使用可编程的模数值。 地址映射器位于查找表的累加器和地址线之间，以将相位累加器值的上升沿和下降沿部分映射到查找表的大区域，而对应于高逻辑电平和低逻辑电平的相位累加器值映射到 查找表的小区域。 所产生的脉冲输出信号容易独立地控制周期和脉冲宽度以及上升和下降沿速度。 通过更好地利用查找表，可以产生具有低重复率或脉冲的非常窄的脉冲，其中上升时间和下降时间与周期非常不同。
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公开(公告)号：US07281025B2
公开(公告)日：2007-10-09
申请号：US10739761
申请日：2003-12-18
IPC分类号： G06F1/02
CPC分类号： G06F1/0328
摘要： A triggered DDS generator architecture accumulates a phase increment value in response to a DDS clock to generate phase accumulator values for addressing a waveform lookup table which contains a desired output signal. A time measurement circuit determines a time interval between the arrival of a trigger signal and a subsequent cycle of the DDS clock, which time interval is used to either adjust an initial phase accumulator value or delay the DDS clock so that a constant time is maintained between the arrival of the trigger signal and the desired output signal.
摘要翻译： 触发的DDS发生器结构响应于DDS时钟积累相位增量值，以产生用于寻址包含期望输出信号的波形查找表的相位累加器值。 时间测量电路确定触发信号的到达和DDS时钟的后续周期之间的时间间隔，该时间间隔用于调整初始相位累加器值或延迟DDS时钟，使得保持恒定时间在 触发信号的到达和所需的输出信号。
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公开(公告)号：US20050138094A1
公开(公告)日：2005-06-23
申请号：US10739761
申请日：2003-12-18
CPC分类号： G06F1/0328
摘要： A triggered DDS generator architecture accumulates a phase increment value in response to a DDS clock to generate phase accumulator values for addressing a waveform lookup table which contains a desired output signal. A time measurement circuit determines a time interval between the arrival of a trigger signal and a subsequent cycle of the DDS clock, which time interval is used to either adjust an initial phase accumulator value or delay the DDS clock so that a constant time is maintained between the arrival of the trigger signal and the desired output signal.
摘要翻译： 触发的DDS发生器结构响应于DDS时钟积累相位增量值，以产生用于寻址包含期望输出信号的波形查找表的相位累加器值。 时间测量电路确定触发信号的到达和DDS时钟的后续周期之间的时间间隔，该时间间隔用于调整初始相位累加器值或延迟DDS时钟，使得保持恒定时间在 触发信号的到达和所需的输出信号。
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公开(公告)号：US20050134330A1
公开(公告)日：2005-06-23
申请号：US10739591
申请日：2003-12-18
CPC分类号： G06F1/0328
摘要： A DDS pulse generator has an accumulator that accumulates a phase increment value to produce phase accumulator values, and has a lookup table that contains a digital representation of a pulse waveform such that a pulse output signal is produced from the lookup table in response to the phase accumulator values. To change a period of the pulse output signal without changing edge positions a programmable modulo value is used. An address mapper is situated between the accumulator and address lines of the lookup table to map the rising and falling edge portions of the phase accumulator values into large regions of the lookup table, while phase accumulator values corresponding to high and low logic levels are mapped into small regions of the lookup table. The resulting pulse output signal has easily independently controlled period and pulse width as well as rising and falling edge speeds. By making better use of the lookup table it is possible to generate very narrow pulses with low repetition rates or pulses in which the rise time and fall time are very different from the period.
摘要翻译： DDS脉冲发生器具有累加相位增量值以产生相位累加器值的累加器，并且具有包含脉冲波形的数字表示的查找表，使得响应于相位从查找表产生脉冲输出信号 累加器值。 为了改变脉冲输出信号的周期而不改变边沿位置，使用可编程的模数值。 地址映射器位于查找表的累加器和地址线之间，以将相位累加器值的上升沿和下降沿部分映射到查找表的大区域，而对应于高逻辑电平和低逻辑电平的相位累加器值映射到 查找表的小区域。 所产生的脉冲输出信号容易独立地控制周期和脉冲宽度以及上升和下降沿速度。 通过更好地利用查找表，可以产生具有低重复率或脉冲的非常窄的脉冲，其中上升时间和下降时间与周期非常不同。
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公开(公告)号：US4403941A
公开(公告)日：1983-09-13
申请号：US175823
申请日：1980-08-05
申请人： Kunio Okiura , Iwao Akiyama , Hiroshi Terada , Yoshijiro Arikawa , Akira Baba , Shigeki Morita
发明人： Kunio Okiura , Iwao Akiyama , Hiroshi Terada , Yoshijiro Arikawa , Akira Baba , Shigeki Morita
CPC分类号： F23C6/047 , F23C2201/101
摘要： A combustion process for reducing nitrogen oxides in combustors is proposed wherein combustion takes place successively forming an incomplete combustion zone, a reducing combustion zone, and a complete combustion zone, respectively corresponding to primary burners, secondary burners and air ports or after-burners, successively arranged in the direction of gas stream in a furnace. According to the present invention, it is possible to reduce nitrogen oxides by improving a manner of combustion without providing any denitrating apparatuses for exhaust gas.
摘要翻译： 提出了一种用于还原燃烧器中的氮氧化物的燃烧方法，其中燃烧依次形成分别对应于初级燃烧器，次燃烧器和空气端口或后燃烧器的不完全燃烧区域，还原燃烧区域和完全燃烧区域， 沿着气流的方向排列在炉中。 根据本发明，可以通过改善燃烧方式来减少氮氧化物，而不需要提供用于废气的任何脱硝设备。
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