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公开(公告)号：US07284025B2
公开(公告)日：2007-10-16
申请号：US10739591
申请日：2003-12-18
IPC分类号： G06F1/02
CPC分类号： G06F1/0328
摘要： A DDS pulse generator has an accumulator that accumulates a phase increment value to produce phase accumulator values, and has a lookup table that contains a digital representation of a pulse waveform such that a pulse output signal is produced from the lookup table in response to the phase accumulator values. To change a period of the pulse output signal without changing edge positions a programmable modulo value is used. An address mapper is situated between the accumulator and address lines of the lookup table to map the rising and falling edge portions of the phase accumulator values into large regions of the lookup table, while phase accumulator values corresponding to high and low logic levels are mapped into small regions of the lookup table. The resulting pulse output signal has easily independently controlled period and pulse width as well as rising and falling edge speeds. By making better use of the lookup table it is possible to generate very narrow pulses with low repetition rates or pulses in which the rise time and fall time are very different from the period.
摘要翻译： DDS脉冲发生器具有累加相位增量值以产生相位累加器值的累加器，并且具有包含脉冲波形的数字表示的查找表，使得响应于相位从查找表产生脉冲输出信号 累加器值。 为了改变脉冲输出信号的周期而不改变边沿位置，使用可编程的模数值。 地址映射器位于查找表的累加器和地址线之间，以将相位累加器值的上升沿和下降沿部分映射到查找表的大区域，而对应于高逻辑电平和低逻辑电平的相位累加器值映射到 查找表的小区域。 所产生的脉冲输出信号容易独立地控制周期和脉冲宽度以及上升和下降沿速度。 通过更好地利用查找表，可以产生具有低重复率或脉冲的非常窄的脉冲，其中上升时间和下降时间与周期非常不同。
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公开(公告)号：US07281025B2
公开(公告)日：2007-10-09
申请号：US10739761
申请日：2003-12-18
IPC分类号： G06F1/02
CPC分类号： G06F1/0328
摘要： A triggered DDS generator architecture accumulates a phase increment value in response to a DDS clock to generate phase accumulator values for addressing a waveform lookup table which contains a desired output signal. A time measurement circuit determines a time interval between the arrival of a trigger signal and a subsequent cycle of the DDS clock, which time interval is used to either adjust an initial phase accumulator value or delay the DDS clock so that a constant time is maintained between the arrival of the trigger signal and the desired output signal.
摘要翻译： 触发的DDS发生器结构响应于DDS时钟积累相位增量值，以产生用于寻址包含期望输出信号的波形查找表的相位累加器值。 时间测量电路确定触发信号的到达和DDS时钟的后续周期之间的时间间隔，该时间间隔用于调整初始相位累加器值或延迟DDS时钟，使得保持恒定时间在 触发信号的到达和所需的输出信号。
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3.发明授权Phase controllable multichannel signal generator having interleaved digital to analog converters 有权具有交错的数模转换器的相位可控多通道信号发生器公开(公告)号：US07941686B2
公开(公告)日：2011-05-10
申请号：US12472244
申请日：2009-05-26
IPC分类号： G06F1/04
CPC分类号： H03L7/00 , H03M1/0624 , H03M1/66
摘要： A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.
摘要翻译： 信号发生器可以控制通道的输出信号之间的相位关系，而不会停止提供给通道的时钟，以使电路运行快速。 第一和第二通道20和22具有分别具有并行到串行转换器和DAC的时钟相移电路26和28的存储器的信号产生块10和12。 相位比较器24比较来自信号发生块10和12的数据读取时钟，以产生相位差信号，其中数据读取时钟用于从信号产生块10和12内的存储器读取波形数据。CPU控制时钟 根据相位差信号将相移电路26和28转换为提供给信号发生块10和12的时钟的相位，然后根据需要使第一和第二通道20和22的输出信号之间产生相位关系。
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公开(公告)号：US20090231005A1
公开(公告)日：2009-09-17
申请号：US12472244
申请日：2009-05-26
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H03M1/0624 , H03M1/66
摘要： A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.
摘要翻译： 信号发生器可以控制通道的输出信号之间的相位关系，而不会停止提供给通道的时钟，以使电路运行快速。 第一和第二通道20和22具有分别具有并行到串行转换器和DAC的时钟相移电路26和28的存储器的信号产生块10和12。 相位比较器24比较来自信号发生块10和12的数据读取时钟，以产生相位差信号，其中数据读取时钟用于从信号产生块10和12内的存储器读取波形数据。CPU控制时钟 根据相位差信号将相移电路26和28转换为提供给信号发生块10和12的时钟的相位，然后根据需要使第一和第二通道20和22的输出信号之间产生相位关系。
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公开(公告)号：US07562246B2
公开(公告)日：2009-07-14
申请号：US11509265
申请日：2006-08-24
IPC分类号： G06F1/04
CPC分类号： H03L7/00 , H03M1/0624 , H03M1/66
摘要： A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.
摘要翻译： 信号发生器可以控制通道的输出信号之间的相位关系，而不会停止提供给通道的时钟，以使电路运行快速。 第一和第二通道20和22具有分别具有并行到串行转换器和DAC的时钟相移电路26和28的存储器的信号产生块10和12。 相位比较器24比较来自信号发生块10和12的数据读取时钟，以产生相位差信号，其中数据读取时钟用于从信号产生块10和12内的存储器读取波形数据。CPU控制时钟 根据相位差信号将相移电路26和28转换为提供给信号发生块10和12的时钟的相位，然后根据需要使第一和第二通道20和22的输出信号之间产生相位关系。
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公开(公告)号：US08872569B2
公开(公告)日：2014-10-28
申请号：US13681278
申请日：2012-11-19
摘要： An automatic quadrature network with amplitude and phase detection produces quadrature signals for an input oscillator signal, the quadrature signals being equal in amplitude and having ideal quadrature phase between them. An RC circuit provides one quadrature path, and a CR circuit provides another quadrature path. The outputs from the RC/CR circuits are amplitude detected to produce an amplitude control signal. The outputs also are amplitude limited, and the phase between the limiter outputs is detected to produce a phase control signal. The amplitude and phase control signals are combined to generate respective control signals for the RC/CR circuits to automatically align them so that the quadrature signals are of equal amplitude and ideal quadrature phase.
摘要翻译： 具有幅度和相位检测的自动正交网络产生用于输入振荡器信号的正交信号，正交信号幅度相等并且在它们之间具有理想的正交相位。 RC电路提供一个正交路径，CR电路提供另一个正交路径。 来自RC / CR电路的输出被振幅检测以产生幅度控制信号。 输出也被限幅，并且检测限幅器输出之间的相位以产生相位控制信号。 振幅和相位控制信号被组合以产生用于RC / CR电路的相应控制信号以自动对准它们，使得正交信号具有相等幅度和理想的正交相位。
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7.发明授权Phase startable clock device for a digitizing instrument having deterministic phase error correction 失效具有确定性相位误差校正的数字化仪器的相位启动时钟装置公开(公告)号：US06411244B1
公开(公告)日：2002-06-25
申请号：US09799743
申请日：2001-03-05
申请人： Laszlo Dobos , Raymond L. Veith
发明人： Laszlo Dobos , Raymond L. Veith
IPC分类号： H03M112
CPC分类号： H03L7/00
摘要： A phase stable clock circuit includes a phase gate having track-and-hold (T/H) circuits with each T/H circuit receiving a phase shifted continuous sinusoidal signal of predetermined phase and a control input signal to capture and hold phase samples of the sinusoidal signals. In alternative embodiments, a phase correction circuit provides phase correction values that are added to the held phase values to generate corrected phase values and time-error phase lookup table is used to generate time position correction values. The corrected phase values are applied to the phase gate remove deterministic phase errors to generate an output signal with a predetermined startup phase relative to the control input signal transition. The phase error-to-time lookup table adjusts the time placement of waveform record samples after the acquisition of the samples. An optional infinite track-and-hold circuit may be used to generate corrected replica phase values that replace the corrected phase values for longer sample delay periods.
摘要翻译： 相位稳定时钟电路包括具有跟踪和保持（T / H）电路的相位门，每个T / H电路接收预定相位的相移连续正弦信号和控制输入信号，以捕获和保持相位采样 正弦信号。 在替代实施例中，相位校正电路提供相位校正值，该相位校正值被添加到所保持的相位值以产生校正的相位值，并且使用时间误差相位查找表来生成时间位置校正值。 校正的相位值被施加到相位栅去除确定性相位误差，以相对于控制输入信号转换产生具有预定起动相位的输出信号。 相位误差查询表调整采样后波形记录采样的时间位置。 可以使用可选的无限跟踪和保持电路来产生校正的副本相位值，以代替更长的采样延迟周期的校正的相位值。
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