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公开(公告)号：US07284025B2
公开(公告)日：2007-10-16
申请号：US10739591
申请日：2003-12-18
IPC分类号： G06F1/02
CPC分类号： G06F1/0328
摘要： A DDS pulse generator has an accumulator that accumulates a phase increment value to produce phase accumulator values, and has a lookup table that contains a digital representation of a pulse waveform such that a pulse output signal is produced from the lookup table in response to the phase accumulator values. To change a period of the pulse output signal without changing edge positions a programmable modulo value is used. An address mapper is situated between the accumulator and address lines of the lookup table to map the rising and falling edge portions of the phase accumulator values into large regions of the lookup table, while phase accumulator values corresponding to high and low logic levels are mapped into small regions of the lookup table. The resulting pulse output signal has easily independently controlled period and pulse width as well as rising and falling edge speeds. By making better use of the lookup table it is possible to generate very narrow pulses with low repetition rates or pulses in which the rise time and fall time are very different from the period.
摘要翻译： DDS脉冲发生器具有累加相位增量值以产生相位累加器值的累加器，并且具有包含脉冲波形的数字表示的查找表，使得响应于相位从查找表产生脉冲输出信号 累加器值。 为了改变脉冲输出信号的周期而不改变边沿位置，使用可编程的模数值。 地址映射器位于查找表的累加器和地址线之间，以将相位累加器值的上升沿和下降沿部分映射到查找表的大区域，而对应于高逻辑电平和低逻辑电平的相位累加器值映射到 查找表的小区域。 所产生的脉冲输出信号容易独立地控制周期和脉冲宽度以及上升和下降沿速度。 通过更好地利用查找表，可以产生具有低重复率或脉冲的非常窄的脉冲，其中上升时间和下降时间与周期非常不同。
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公开(公告)号：US07281025B2
公开(公告)日：2007-10-09
申请号：US10739761
申请日：2003-12-18
IPC分类号： G06F1/02
CPC分类号： G06F1/0328
摘要： A triggered DDS generator architecture accumulates a phase increment value in response to a DDS clock to generate phase accumulator values for addressing a waveform lookup table which contains a desired output signal. A time measurement circuit determines a time interval between the arrival of a trigger signal and a subsequent cycle of the DDS clock, which time interval is used to either adjust an initial phase accumulator value or delay the DDS clock so that a constant time is maintained between the arrival of the trigger signal and the desired output signal.
摘要翻译： 触发的DDS发生器结构响应于DDS时钟积累相位增量值，以产生用于寻址包含期望输出信号的波形查找表的相位累加器值。 时间测量电路确定触发信号的到达和DDS时钟的后续周期之间的时间间隔，该时间间隔用于调整初始相位累加器值或延迟DDS时钟，使得保持恒定时间在 触发信号的到达和所需的输出信号。
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3.发明授权Phase controllable multichannel signal generator having interleaved digital to analog converters 有权具有交错的数模转换器的相位可控多通道信号发生器公开(公告)号：US07941686B2
公开(公告)日：2011-05-10
申请号：US12472244
申请日：2009-05-26
IPC分类号： G06F1/04
CPC分类号： H03L7/00 , H03M1/0624 , H03M1/66
摘要： A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.
摘要翻译： 信号发生器可以控制通道的输出信号之间的相位关系，而不会停止提供给通道的时钟，以使电路运行快速。 第一和第二通道20和22具有分别具有并行到串行转换器和DAC的时钟相移电路26和28的存储器的信号产生块10和12。 相位比较器24比较来自信号发生块10和12的数据读取时钟，以产生相位差信号，其中数据读取时钟用于从信号产生块10和12内的存储器读取波形数据。CPU控制时钟 根据相位差信号将相移电路26和28转换为提供给信号发生块10和12的时钟的相位，然后根据需要使第一和第二通道20和22的输出信号之间产生相位关系。
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公开(公告)号：US20090231005A1
公开(公告)日：2009-09-17
申请号：US12472244
申请日：2009-05-26
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H03M1/0624 , H03M1/66
摘要： A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.
摘要翻译： 信号发生器可以控制通道的输出信号之间的相位关系，而不会停止提供给通道的时钟，以使电路运行快速。 第一和第二通道20和22具有分别具有并行到串行转换器和DAC的时钟相移电路26和28的存储器的信号产生块10和12。 相位比较器24比较来自信号发生块10和12的数据读取时钟，以产生相位差信号，其中数据读取时钟用于从信号产生块10和12内的存储器读取波形数据。CPU控制时钟 根据相位差信号将相移电路26和28转换为提供给信号发生块10和12的时钟的相位，然后根据需要使第一和第二通道20和22的输出信号之间产生相位关系。
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公开(公告)号：US07562246B2
公开(公告)日：2009-07-14
申请号：US11509265
申请日：2006-08-24
IPC分类号： G06F1/04
CPC分类号： H03L7/00 , H03M1/0624 , H03M1/66
摘要： A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.
摘要翻译： 信号发生器可以控制通道的输出信号之间的相位关系，而不会停止提供给通道的时钟，以使电路运行快速。 第一和第二通道20和22具有分别具有并行到串行转换器和DAC的时钟相移电路26和28的存储器的信号产生块10和12。 相位比较器24比较来自信号发生块10和12的数据读取时钟，以产生相位差信号，其中数据读取时钟用于从信号产生块10和12内的存储器读取波形数据。CPU控制时钟 根据相位差信号将相移电路26和28转换为提供给信号发生块10和12的时钟的相位，然后根据需要使第一和第二通道20和22的输出信号之间产生相位关系。
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公开(公告)号：US20050138094A1
公开(公告)日：2005-06-23
申请号：US10739761
申请日：2003-12-18
CPC分类号： G06F1/0328
摘要： A triggered DDS generator architecture accumulates a phase increment value in response to a DDS clock to generate phase accumulator values for addressing a waveform lookup table which contains a desired output signal. A time measurement circuit determines a time interval between the arrival of a trigger signal and a subsequent cycle of the DDS clock, which time interval is used to either adjust an initial phase accumulator value or delay the DDS clock so that a constant time is maintained between the arrival of the trigger signal and the desired output signal.
摘要翻译： 触发的DDS发生器结构响应于DDS时钟积累相位增量值，以产生用于寻址包含期望输出信号的波形查找表的相位累加器值。 时间测量电路确定触发信号的到达和DDS时钟的后续周期之间的时间间隔，该时间间隔用于调整初始相位累加器值或延迟DDS时钟，使得保持恒定时间在 触发信号的到达和所需的输出信号。
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公开(公告)号：US20050134330A1
公开(公告)日：2005-06-23
申请号：US10739591
申请日：2003-12-18
CPC分类号： G06F1/0328
摘要： A DDS pulse generator has an accumulator that accumulates a phase increment value to produce phase accumulator values, and has a lookup table that contains a digital representation of a pulse waveform such that a pulse output signal is produced from the lookup table in response to the phase accumulator values. To change a period of the pulse output signal without changing edge positions a programmable modulo value is used. An address mapper is situated between the accumulator and address lines of the lookup table to map the rising and falling edge portions of the phase accumulator values into large regions of the lookup table, while phase accumulator values corresponding to high and low logic levels are mapped into small regions of the lookup table. The resulting pulse output signal has easily independently controlled period and pulse width as well as rising and falling edge speeds. By making better use of the lookup table it is possible to generate very narrow pulses with low repetition rates or pulses in which the rise time and fall time are very different from the period.
摘要翻译： DDS脉冲发生器具有累加相位增量值以产生相位累加器值的累加器，并且具有包含脉冲波形的数字表示的查找表，使得响应于相位从查找表产生脉冲输出信号 累加器值。 为了改变脉冲输出信号的周期而不改变边沿位置，使用可编程的模数值。 地址映射器位于查找表的累加器和地址线之间，以将相位累加器值的上升沿和下降沿部分映射到查找表的大区域，而对应于高逻辑电平和低逻辑电平的相位累加器值映射到 查找表的小区域。 所产生的脉冲输出信号容易独立地控制周期和脉冲宽度以及上升和下降沿速度。 通过更好地利用查找表，可以产生具有低重复率或脉冲的非常窄的脉冲，其中上升时间和下降时间与周期非常不同。
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公开(公告)号：US5424667A
公开(公告)日：1995-06-13
申请号：US962974
申请日：1992-10-15
申请人： Ryoichi Sakai , Iwao Akiyama , Yasumasa Fujisawa
发明人： Ryoichi Sakai , Iwao Akiyama , Yasumasa Fujisawa
CPC分类号： G06F1/0328 , G06F2101/04
摘要： A DDS type variable frequency signal generator generates a jitter free and stable output signal regardless of the address interval. If the total number of addressable memory locations of a memory storing digital data is divisible without remainder by an initial address interval, then the memory is read every initial address interval with a clock signal of a predetermined frequency. If the total number of addressable memory locations is not divisible without remainder by the initial address interval, then the address interval is modified to a value that is divisible without remainder into the total number of addressable memory locations and the clock frequency is modified in accordance with this modification of the address interval. The memory is read every modified address interval with the modified clock signal.
摘要翻译： 无论地址间隔如何，DDS型可变频率信号发生器产生无抖动和稳定的输出信号。 如果存储数字数据的存储器的可寻址存储器位置的总数可被除以初始地址间隔的余数，则以每个初始地址间隔读取具有预定频率的时钟信号的存储器。 如果可寻址存储器位置的总数不能被除以初始地址间隔的余数，则地址间隔被修改为可以被除去的值，而没有余数到可寻址存储器位置的总数中，并且时钟频率根据 这个地址间隔的修改。 每个修改的地址间隔读取存储器与修改的时钟信号。
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公开(公告)号：US20070046349A1
公开(公告)日：2007-03-01
申请号：US11509265
申请日：2006-08-24
申请人： Yasumasa Fujisawa , Raymond Veith
发明人： Yasumasa Fujisawa , Raymond Veith
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H03M1/0624 , H03M1/66
摘要： A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.
摘要翻译： 信号发生器可以控制通道的输出信号之间的相位关系，而不会停止提供给通道的时钟，以使电路运行快速。 第一和第二通道20和22具有分别具有并行到串行转换器和DAC的时钟相移电路26和28的存储器的信号产生块10和12。 相位比较器24比较来自信号发生块10和12的数据读取时钟，以产生相位差信号，其中数据读取时钟用于从信号产生块10和12内的存储器读取波形数据。CPU控制时钟 根据相位差信号将相移电路26和28转换为提供给信号发生块10和12的时钟的相位，然后根据需要使第一和第二通道20和22的输出信号之间产生相位关系。
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公开(公告)号：US07890679B2
公开(公告)日：2011-02-15
申请号：US11264985
申请日：2005-11-01
申请人： Yasumasa Fujisawa
发明人： Yasumasa Fujisawa
CPC分类号： G06F13/4018 , H03M9/00
摘要： A data generator provides faster data than before. A parallel data generator 18 provides first data having four or five effective data width according to a divided clock DCLK. A bit width adjuster 20 having a FIFO memory receives the first parallel data to provide second parallel data of constant four bit width despite of the bit width of the first parallel data. A parallel to serial converter 12 converts the second parallel data into serial data according to a reference clock RCLK that is faster than divided clock DCLK. The frequency of the divided clock DCLK can be constant, which makes it possible to use DLL to fasten the operation of the logic circuits.
摘要翻译： 数据生成器提供比以前更快的数据。 并行数据发生器18根据划分的时钟DCLK提供具有四个或五个有效数据宽度的第一数据。 具有FIFO存储器的位宽调整器20接收第一并行数据以提供恒定的四位宽度的第二并行数据，而不管第一并行数据的位宽。 并行到串行转换器12根据比分频时钟DCLK更快的参考时钟RCLK将第二并行数据转换为串行数据。 分频时钟DCLK的频率可以是常数，这使得可以使用DLL来紧固逻辑电路的操作。
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