公开(公告)号：US20050216869A1

公开(公告)日：2005-09-29

申请号：US11087752

申请日：2005-03-24

申请人： Ryoko Miyachi ,  Tomoo Hamada ,  Hajime Ogawa ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

发明人： Ryoko Miyachi ,  Tomoo Hamada ,  Hajime Ogawa ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

IPC分类号： G06F17/50

CPC分类号： G06F8/423 ,  G06F17/505

摘要： A compiler apparatus enabling description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.

摘要翻译： 尽管在硬件设计中输入编程语言的描述是不可能的，但是使用现有编程语言来描述特定硬件模块的编译器装置。 在头文件24中，定义了难以形容的编程语言中的特定硬件。 并且编译装置包括分析源程序22的语法的解析器单元30，将语法分析的源程序22转换成将中间代码转换为RTL描述的中间代码和代码生成单元36的中间代码转换单元32。 中间代码转换单元32包括检测单元40，其检测来自源程序22中的头文件24中定义的特定硬件;以及替换单元42，用检测单元40中的检测到的特定硬件替换与特定的对应的中间代码 硬件。

公开(公告)号：US07350165B2

公开(公告)日：2008-03-25

申请号：US11087752

申请日：2005-03-24

申请人： Ryoko Miyachi ,  Tomoo Hamada ,  Hajime Ogawa ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

发明人： Ryoko Miyachi ,  Tomoo Hamada ,  Hajime Ogawa ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

IPC分类号： G06F17/50

CPC分类号： G06F8/423 ,  G06F17/505

摘要： A compiler apparatus enables description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.

摘要翻译： 编译装置能够描述现有编程语言中的特定硬件模块，尽管在硬件设计中输入编程语言的描述是不可能的。 在头文件24中，定义了难以形容的编程语言中的特定硬件。 并且编译装置包括分析源程序22的语法的解析器单元30，将语法分析的源程序22转换成将中间代码转换为RTL描述的中间代码和代码生成单元36的中间代码转换单元32。 中间代码转换单元32包括检测单元40，其检测来自源程序22中的头文件24中定义的特定硬件;以及替换单元42，用检测单元40中的检测到的特定硬件替换与特定的对应的中间代码 硬件。

公开(公告)号：US20060150135A1

公开(公告)日：2006-07-06

申请号：US11290806

申请日：2005-12-01

申请人： Tomoo Hamada ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

发明人： Tomoo Hamada ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Provided is an apparatus for generating circuit design information automatically clock gated, for the purpose of alleviating the burden of a designer in performing clock gating to a circuit. The apparatus having an obtaining unit operable to obtain functional structure information and execution sequence information from outside, the functional structure information defining a structure of a function and the execution sequence information defining an execution sequence of the function; a structure information generating unit operable to generate, according to the execution sequence information and the functional structure information, circuit structure information in register transfer level which defines a plurality of circuits that execute the function according to the execution sequence; a gated clock information generating unit operable to generate, according to the execution sequence information and the functional structure information, gated clock information in register transfer level which defines a clock control circuit that supplies, to each of at least one of the circuits, a gated clock that is set to halt clock input when the clock input is unnecessary; and an outputting unit operable to output the gated clock information together with the circuit structure information.

摘要翻译： 提供了一种用于自动生成电路设计信息时钟门控的装置，用于减轻设计者对电路执行时钟门控的负担。 该装置具有可从外部获取功能结构信息和执行序列信息的获取单元，定义功能结构的功能结构信息和定义功能的执行顺序的执行顺序信息; 结构信息生成单元，用于根据执行顺序信息和功能结构信息生成根据执行顺序定义执行功能的多个电路的寄存器传送等级的电路结构信息; 门控时钟信息生成单元，其可操作以根据执行顺序信息和功能结构信息生成寄存器传送级别中的门控时钟信息，其定义时钟控制电路，该时钟控制电路向至少一个电路中的每一个提供门控 当不需要时钟输入时，设置为暂停时钟输入的时钟; 以及输出单元，用于将门控时钟信息与电路结构信息一起输出。

公开(公告)号：US07571432B2

公开(公告)日：2009-08-04

申请号：US10944831

申请日：2004-09-21

申请人： Taketo Heishi ,  Hajime Ogawa ,  Yasuhiro Yamamoto ,  Kyoko Hattori ,  Shohei Michimoto ,  Kenji Hattori ,  Hirotetsu Tomita ,  Teruo Kawabata ,  Kiyoshi Nakashima

发明人： Taketo Heishi ,  Hajime Ogawa ,  Yasuhiro Yamamoto ,  Kyoko Hattori ,  Shohei Michimoto ,  Kenji Hattori ,  Hirotetsu Tomita ,  Teruo Kawabata ,  Kiyoshi Nakashima

IPC分类号： G06F9/45

CPC分类号： G06F8/4442

摘要： A compiler 58, which is a compiler that realizes program development in a fewer man hours, translates a source program 72 written in a high-level language into a machine language program. This compiler 58 is comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unit 76 that parses the source program 72; an intermediate code conversion unit 78 that converts the source program 72 into intermediate codes based on a result of the parsing performed by the parser unit 76; an optimization unit 68 that optimizes the intermediate codes according to the directive; and a code generation unit 90 that converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.

摘要翻译： 编译器58是以较少的工时实现程序开发的编译器，将以高级语言编写的源程序72翻译成机器语言程序。 该编译器58包括：指令获取单元，其获得应当优化要生成的机器语言程序的指令; 解析源程序72的解析器单元76; 中间代码转换单元78，其基于由解析器单元76执行的解析的结果将源程序72转换为中间代码; 优化单元68，根据该指令优化中间代码; 以及将中间代码转换为机器语言程序的代码生成单元90。 上述指令是优化针对使用高速缓存的处理器的机器语言程序的指令。

公开(公告)号：US20050086653A1

公开(公告)日：2005-04-21

申请号：US10944831

申请日：2004-09-21

申请人： Taketo Heishi ,  Hajime Ogawa ,  Yasuhiro Yamamoto ,  Kyoko Hattori ,  Shohei Michimoto ,  Kenji Hattori ,  Hirotetsu Tomita ,  Teruo Kawabata ,  Kiyoshi Nakashima

发明人： Taketo Heishi ,  Hajime Ogawa ,  Yasuhiro Yamamoto ,  Kyoko Hattori ,  Shohei Michimoto ,  Kenji Hattori ,  Hirotetsu Tomita ,  Teruo Kawabata ,  Kiyoshi Nakashima

IPC分类号： G06F9/45

CPC分类号： G06F8/4442

摘要： A compiler 58, which is a compiler that realizes program development in a fewer man hours, translates a source program 72 written in a high-level language into a machine language program. This compiler 58 is comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unit 76 that parses the source program 72; an intermediate code conversion unit 78 that converts the source program 72 into intermediate codes based on a result of the parsing performed by the parser unit 76; an optimization unit 68 that optimizes the intermediate codes according to the directive; and a code generation unit 90 that converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.

摘要翻译： 编译器58是以较少的工时实现程序开发的编译器，将以高级语言编写的源程序72翻译成机器语言程序。 该编译器58包括：指令获取单元，其获得应当优化要生成的机器语言程序的指令; 解析源程序72的解析器单元76; 中间代码转换单元78，其基于由解析器单元76执行的解析的结果将源程序72转换为中间代码; 优化单元68，根据该指令优化中间代码; 以及将中间代码转换为机器语言程序的代码生成单元90。 上述指令是优化针对使用高速缓存的处理器的机器语言程序的指令。

公开(公告)号：US20060107267A1

公开(公告)日：2006-05-18

申请号：US11270515

申请日：2005-11-10

申请人： Ryoko Miyachi ,  Hajime Ogawa ,  Tomoo Hamada ,  Teruo Kawabata

发明人： Ryoko Miyachi ,  Hajime Ogawa ,  Tomoo Hamada ,  Teruo Kawabata

IPC分类号： G06F9/46

CPC分类号： G06F17/505

摘要： An instruction scheduling method according to the present invention allocates each instruction included in an instruction sequence to be synthesized as a circuit to one of execution cycles in the circuit, and includes: detecting a freedom of each instruction, the freedom representing a time period within which the instruction can be allocated; calculating a load of a processing element corresponding to the instruction for each of the execution cycles; and allocating the instructions using the same processing element within the freedoms to different execution cycles based on the load.

摘要翻译： 根据本发明的指令调度方法将要合成的指令序列中包括的每个指令分配给电路中的一个执行周期，并且包括：检测每个指令的自由度，表示其中的自由度，其中 该指令可以分配; 计算与每个执行周期的指令相对应的处理元件的负载; 以及基于所述负载，在所述自由度内使用相同处理元件将指令分配给不同的执行周期。

公开(公告)号：US20060248520A1

公开(公告)日：2006-11-02

申请号：US10565530

申请日：2005-02-04

申请人： Teruo Kawabata ,  Hajime Ogawa ,  Taketo Heishi ,  Yasuhiro Yamamoto ,  Shohei Michimoto

发明人： Teruo Kawabata ,  Hajime Ogawa ,  Taketo Heishi ,  Yasuhiro Yamamoto ,  Shohei Michimoto

IPC分类号： G06F9/45

CPC分类号： G06F8/443

摘要： A compiler which improves the processing speed of a program execution without needlessly issuing an instruction that has a possibility of causing an interlock is targeted at a processor having an instruction that has a possibility of causing an interlock when the instruction is executed, the compiler causing a computer to function as: a loop structure transforming unit (186) which performs double looping transformation on an input program so that a loop whose iteration count is y is split off from a loop whose loop count is x and the loop whose iteration count is y is an inner loop whereas a loop whose iteration count is x/y is an outer loop; and an instruction optimum placing unit (187) which places an instruction that has a possibility of causing an interlock in the program on which the double looping transformation has been performed.

摘要翻译： 一种改进程序执行的处理速度而不用不必要地发出具有引起互锁的可能性的指令的编译器针对具有在执行指令时可能引起互锁的指令的处理器，编译器引起 计算机用作：循环结构变换单元（186），其对输入程序执行双循环变换，使得迭代计数为y的循环与循环计数为x的循环和迭代计数为y的循环分离 是一个内循环，而迭代计数为x / y的循环是一个外循环; 以及指令最佳放置单元（187），其放置在执行了双重循环变换的程序中具有引起互锁的可能性的指令。

公开(公告)号：USRE45199E1

公开(公告)日：2014-10-14

申请号：US13616573

申请日：2012-09-14

申请人： Shohei Michimoto ,  Taketo Heishi ,  Hajime Ogawa ,  Teruo Kawabata

发明人： Shohei Michimoto ,  Taketo Heishi ,  Hajime Ogawa ,  Teruo Kawabata

IPC分类号： G06F9/45

CPC分类号： G06F8/4452 ,  G06F8/433

摘要： A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.

摘要翻译： 可以执行软件流水线优化的编译器装置，其具有减少完成循环处理所执行的执行周期的数量的显着效果，将源程序转换为能够并行处理的处理器的机器程序。 编译装置由以下部分组成：解析单元，用于解析源程序，然后将源程序转换成以中间语言描述的中间程序; 可优化所述中间程序的优化单元; 以及转换单元，其可操作以将优化的中间程序转换成机器语言程序，其中所述优化单元可操作以通过将用于在操作数之间传送数据的传送指令插入到包括在所述机器语言程序中的循环处理中来执行软件流水线 中间程序，使数据依赖关系发生变化。

公开(公告)号：US07856629B2

公开(公告)日：2010-12-21

申请号：US11420059

申请日：2006-05-24

申请人： Shohei Michimoto ,  Taketo Heishi ,  Hajime Ogawa ,  Teruo Kawabata

发明人： Shohei Michimoto ,  Taketo Heishi ,  Hajime Ogawa ,  Teruo Kawabata

IPC分类号： G06F9/45

CPC分类号： G06F8/4452 ,  G06F8/433

摘要： A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.

摘要翻译： 可以执行软件流水线优化的编译器装置，其具有减少完成循环处理所执行的执行周期的数量的显着效果，将源程序转换为能够并行处理的处理器的机器程序。 编译装置由以下部分组成：解析单元，用于解析源程序，然后将源程序转换成以中间语言描述的中间程序; 可优化所述中间程序的优化单元; 以及转换单元，其可操作以将优化的中间程序转换成机器语言程序，其中所述优化单元可操作以通过将用于在操作数之间传送数据的传送指令插入到包括在所述机器语言程序中的循环处理中来执行软件流水线 中间程序，使数据依赖关系发生变化。

公开(公告)号：US08612958B2

公开(公告)日：2013-12-17

申请号：US13163035

申请日：2011-06-17

申请人： Taketo Heishi ,  Shohei Michimoto ,  Teruo Kawabata

发明人： Taketo Heishi ,  Shohei Michimoto ,  Teruo Kawabata

IPC分类号： G06F9/45

CPC分类号： G06F8/445 ,  G06F8/314

摘要： A compiler, which corresponds to a recent processor having a multithread function, that enables execution of efficient instruction scheduling and allows a programmer to control the instruction scheduling includes: an instruction scheduling directive receiving unit which receives, from a programmer, a directive for specifying an instruction scheduling method; and an instruction scheduling unit which executes, conforming to one of instruction scheduling methods, instruction scheduling of rearranging intermediate codes corresponding to the source program. The instruction scheduling unit selects one of instruction scheduling methods according to the directive received by the instruction scheduling directive receiving unit, and executes instruction scheduling conforming to the selected instruction scheduling method.

摘要翻译： 一种编译器，其对应于具有多线程功能的最近的处理器，其能够执行有效的指令调度并允许程序员控制指令调度包括：指令调度指令接收单元，其从程序员接收用于指定 指令调度方法; 以及指令调度单元，其执行符合指令调度方法之一的重新排列与源程序对应的中间代码的指令调度。 指令调度单元根据指令调度指示接收单元接收的指令选择指令调度方法之一，并执行符合所选指令调度方法的指令调度。