公开(公告)号：US20050216869A1

公开(公告)日：2005-09-29

申请号：US11087752

申请日：2005-03-24

申请人： Ryoko Miyachi ,  Tomoo Hamada ,  Hajime Ogawa ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

发明人： Ryoko Miyachi ,  Tomoo Hamada ,  Hajime Ogawa ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

IPC分类号： G06F17/50

CPC分类号： G06F8/423 ,  G06F17/505

摘要： A compiler apparatus enabling description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.

摘要翻译： 尽管在硬件设计中输入编程语言的描述是不可能的，但是使用现有编程语言来描述特定硬件模块的编译器装置。 在头文件24中，定义了难以形容的编程语言中的特定硬件。 并且编译装置包括分析源程序22的语法的解析器单元30，将语法分析的源程序22转换成将中间代码转换为RTL描述的中间代码和代码生成单元36的中间代码转换单元32。 中间代码转换单元32包括检测单元40，其检测来自源程序22中的头文件24中定义的特定硬件;以及替换单元42，用检测单元40中的检测到的特定硬件替换与特定的对应的中间代码 硬件。

公开(公告)号：US07350165B2

公开(公告)日：2008-03-25

申请号：US11087752

申请日：2005-03-24

申请人： Ryoko Miyachi ,  Tomoo Hamada ,  Hajime Ogawa ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

发明人： Ryoko Miyachi ,  Tomoo Hamada ,  Hajime Ogawa ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

IPC分类号： G06F17/50

CPC分类号： G06F8/423 ,  G06F17/505

摘要： A compiler apparatus enables description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.

摘要翻译： 编译装置能够描述现有编程语言中的特定硬件模块，尽管在硬件设计中输入编程语言的描述是不可能的。 在头文件24中，定义了难以形容的编程语言中的特定硬件。 并且编译装置包括分析源程序22的语法的解析器单元30，将语法分析的源程序22转换成将中间代码转换为RTL描述的中间代码和代码生成单元36的中间代码转换单元32。 中间代码转换单元32包括检测单元40，其检测来自源程序22中的头文件24中定义的特定硬件;以及替换单元42，用检测单元40中的检测到的特定硬件替换与特定的对应的中间代码 硬件。

公开(公告)号：US20060150135A1

公开(公告)日：2006-07-06

申请号：US11290806

申请日：2005-12-01

申请人： Tomoo Hamada ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

发明人： Tomoo Hamada ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Provided is an apparatus for generating circuit design information automatically clock gated, for the purpose of alleviating the burden of a designer in performing clock gating to a circuit. The apparatus having an obtaining unit operable to obtain functional structure information and execution sequence information from outside, the functional structure information defining a structure of a function and the execution sequence information defining an execution sequence of the function; a structure information generating unit operable to generate, according to the execution sequence information and the functional structure information, circuit structure information in register transfer level which defines a plurality of circuits that execute the function according to the execution sequence; a gated clock information generating unit operable to generate, according to the execution sequence information and the functional structure information, gated clock information in register transfer level which defines a clock control circuit that supplies, to each of at least one of the circuits, a gated clock that is set to halt clock input when the clock input is unnecessary; and an outputting unit operable to output the gated clock information together with the circuit structure information.

摘要翻译： 提供了一种用于自动生成电路设计信息时钟门控的装置，用于减轻设计者对电路执行时钟门控的负担。 该装置具有可从外部获取功能结构信息和执行序列信息的获取单元，定义功能结构的功能结构信息和定义功能的执行顺序的执行顺序信息; 结构信息生成单元，用于根据执行顺序信息和功能结构信息生成根据执行顺序定义执行功能的多个电路的寄存器传送等级的电路结构信息; 门控时钟信息生成单元，其可操作以根据执行顺序信息和功能结构信息生成寄存器传送级别中的门控时钟信息，其定义时钟控制电路，该时钟控制电路向至少一个电路中的每一个提供门控 当不需要时钟输入时，设置为暂停时钟输入的时钟; 以及输出单元，用于将门控时钟信息与电路结构信息一起输出。

公开(公告)号：US07698696B2

公开(公告)日：2010-04-13

申请号：US10608040

申请日：2003-06-30

申请人： Hajime Ogawa ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

发明人： Hajime Ogawa ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F8/443

摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.

摘要翻译： 编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元， 根据来自分析单元等的指令等，执行由用户选择和编译指定的单独优化处理的“if”转换单元和一对指令生成单元）。全局区域分配单元执行优化处理 指定要分配给全球区域的变量的最大数据大小，指定要分配给全局区域的变量，以及关于指定未分配给全局区域的变量的选项和编译指示。

公开(公告)号：US08418157B2

公开(公告)日：2013-04-09

申请号：US12706329

申请日：2010-02-16

申请人： Hajime Ogawa ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

发明人： Hajime Ogawa ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

IPC分类号： G06F9/45

CPC分类号： G06F8/443

摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.

摘要翻译： 编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元， 如果转换单元和配对指令生成单元）执行来自用户的选项和编译指示的单独优化处理，遵循来自分析单元的指令等。全局区域分配单元执行优化处理，在指定 要分配给全局区域的变量的最大数据大小，要分配给全局区域的变量的指定，以及关于在全局区域中未分配的变量的指定的选项和编译指示。

公开(公告)号：US20100175056A1

公开(公告)日：2010-07-08

申请号：US12706329

申请日：2010-02-16

申请人： Hajime OGAWA ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

发明人： Hajime OGAWA ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F8/443

摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.

摘要翻译： 编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元， 根据来自分析单元等的指令等，执行由用户选择和编译指定的单独优化处理的“if”转换单元和一对指令生成单元）。全局区域分配单元执行优化处理 指定要分配给全球区域的变量的最大数据大小，指定要分配给全局区域的变量，以及关于指定未分配给全局区域的变量的选项和编译指示。

公开(公告)号：US20060107267A1

公开(公告)日：2006-05-18

申请号：US11270515

申请日：2005-11-10

申请人： Ryoko Miyachi ,  Hajime Ogawa ,  Tomoo Hamada ,  Teruo Kawabata

发明人： Ryoko Miyachi ,  Hajime Ogawa ,  Tomoo Hamada ,  Teruo Kawabata

IPC分类号： G06F9/46

CPC分类号： G06F17/505

摘要： An instruction scheduling method according to the present invention allocates each instruction included in an instruction sequence to be synthesized as a circuit to one of execution cycles in the circuit, and includes: detecting a freedom of each instruction, the freedom representing a time period within which the instruction can be allocated; calculating a load of a processing element corresponding to the instruction for each of the execution cycles; and allocating the instructions using the same processing element within the freedoms to different execution cycles based on the load.

摘要翻译： 根据本发明的指令调度方法将要合成的指令序列中包括的每个指令分配给电路中的一个执行周期，并且包括：检测每个指令的自由度，表示其中的自由度，其中 该指令可以分配; 计算与每个执行周期的指令相对应的处理元件的负载; 以及基于所述负载，在所述自由度内使用相同处理元件将指令分配给不同的执行周期。

公开(公告)号：US20100199269A1

公开(公告)日：2010-08-05

申请号：US12668967

申请日：2008-10-08

申请人： Dai Hattori ,  Tomoo Hamada

发明人： Dai Hattori ,  Tomoo Hamada

IPC分类号： G06F9/45

CPC分类号： G06F8/443

摘要： A program optimization device which, when optimizing a program, performs optimization depending on characteristics of data to be processed by the program without having to execute the program before the optimization, includes: an intermediate code conversion unit that converts an input program to be optimized, into an intermediate code; a variable value setting unit that sets a possible value of a variable according to externally provided information; a node value calculation unit that calculates a possible value of a node included in the intermediate code according to the value set by the variable value setting unit; an intermediate code optimization unit that optimizes the intermediate code according to the value calculated by the node value calculation unit; and an output program conversion unit that converts the intermediate code optimized by the intermediate code optimization unit, to an output program.

摘要翻译： 一种程序优化装置，当优化程序时，根据程序要处理的数据的特性执行优化，而不必在优化之前执行程序，包括：中间代码转换单元，其转换要优化的输入程序， 成为中间代码 可变值设定单元，根据外部提供的信息设定变量的可能值; 节点值计算单元，根据由所述可变值设定单元设定的值，计算包含在所述中间代码中的节点的可能值; 中间代码优化单元，其根据由所述节点值计算单元计算出的值来优化所述中间代码; 以及输出程序转换单元，其将由中间代码优化单元优化的中间代码转换为输出程序。

公开(公告)号：US20060212440A1

公开(公告)日：2006-09-21

申请号：US11370859

申请日：2006-03-09

申请人： Taketo Heishi ,  Tomoo Hamada

发明人： Taketo Heishi ,  Tomoo Hamada

IPC分类号： G06F17/30

CPC分类号： G06F8/4442

摘要： In a development of system software, a compiler system and the like are included in a program development system for increasing performance efficiency of an overall computer system and reducing manpower necessary for developing system software. The compiler system is a program for reading a source program and system level hint information and translating them into a machine language program, generating the machine language program and outputting task information that is information relating to the program. The system level hint information is a collection of information that become hints for optimization performed in the compiler system, and is made up of an analysis result obtained by a profiler, an instruction from a programmer, task information relating to the source program and task information relating to another source program that is different from the source program.

摘要翻译： 在系统软件的开发中，编译系统等被包括在程序开发系统中，以提高整个计算机系统的性能效率并减少开发系统软件所需的人力。 编译器系统是用于读取源程序和系统级提示信息并将其转换为机器语言程序的程序，生成机器语言程序并输出与程序相关的信息的任务信息。 系统级提示信息是在编译器系统中作为优化的提示的信息的集合，并且由分析器获得的分析结果，来自程序员的指令，与源程序相关的任务信息和任务信息 涉及与源程序不同的另一个源程序。