公开(公告)号：US20110298990A1

公开(公告)日：2011-12-08

申请号：US13214649

申请日：2011-08-22

申请人： Yasuhiro ISHII ,  Shuichi TAKAYAMA ,  Ryoko MIYACHI

发明人： Yasuhiro ISHII ,  Shuichi TAKAYAMA ,  Ryoko MIYACHI

IPC分类号： H04N5/50

CPC分类号： H04N5/44591 ,  H04N5/4401 ,  H04N21/23424 ,  H04N21/4331 ,  H04N21/4345 ,  H04N21/44016 ,  H04N21/812

摘要： A digital broadcast receiving apparatus includes a channel selection control unit selecting a channel of a digital broadcast, a demultiplexing unit and a video decoder obtaining video data and data broadcast data from electrical wave of the digital broadcast of the channel selected by the channel selection control unit, a data broadcast accumulation unit accumulating the data broadcast data obtained by the acquisition unit for each channel, and a rendering unit and a video composition unit generating composite video data by reading out the data broadcast data of at least one channel that includes a channel different from a channel of the video data obtained by the acquisition unit from the data broadcast accumulation unit and combining the readout data broadcast data and the video data obtained by the acquisition unit.

摘要翻译： 数字广播接收装置包括选择数字广播的频道的频道选择控制单元，解复用单元和视频解码器，从频道选择控制单元选择的频道的数字广播的电波获取视频数据和数据广播数据 ，累积由每个通道的获取单元获得的数据广播数据的数据广播累积单元，以及通过读出包括不同信道的信道的至少一个信道的数据广播数据来生成复合视频数据的再现单元和视频合成单元 从所述获取单元从所述数据广播累积单元获得的视频数据的频道，并将读出的数据广播数据和由所述获取单元获得的视频数据组合。

公开(公告)号：US07284241B2

公开(公告)日：2007-10-16

申请号：US10630705

申请日：2003-07-31

申请人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

发明人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

IPC分类号： G06F9/45

CPC分类号： G06F8/443 ,  G06F8/425 ,  G06F8/427 ,  G06F8/4441

摘要： An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.

摘要翻译： 提供包括在源程序101中的操作者定义文件102等以及将源程序101转换为机器语言程序105的编译器100。 操作者定义文件102包括通过类定义的各种定点类型操作符的定义。 编译器100可以生成有效的高级特定指令，处理器执行并通过扩展功能等进行改进，而不会重复频繁升级编译器本身的版本。 编译器100由生成中间代码的中间代码生成单元121构成，机器语言指令替换单元122，其使用机器语言指令代替参考由操作者定义文件102定义的类别的中间代码和优化单元130， 执行针对包括替代机器语言指令的中间代码的优化。

公开(公告)号：US20050216869A1

公开(公告)日：2005-09-29

申请号：US11087752

申请日：2005-03-24

申请人： Ryoko Miyachi ,  Tomoo Hamada ,  Hajime Ogawa ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

发明人： Ryoko Miyachi ,  Tomoo Hamada ,  Hajime Ogawa ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

IPC分类号： G06F17/50

CPC分类号： G06F8/423 ,  G06F17/505

摘要： A compiler apparatus enabling description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.

摘要翻译： 尽管在硬件设计中输入编程语言的描述是不可能的，但是使用现有编程语言来描述特定硬件模块的编译器装置。 在头文件24中，定义了难以形容的编程语言中的特定硬件。 并且编译装置包括分析源程序22的语法的解析器单元30，将语法分析的源程序22转换成将中间代码转换为RTL描述的中间代码和代码生成单元36的中间代码转换单元32。 中间代码转换单元32包括检测单元40，其检测来自源程序22中的头文件24中定义的特定硬件;以及替换单元42，用检测单元40中的检测到的特定硬件替换与特定的对应的中间代码 硬件。

公开(公告)号：US07698696B2

公开(公告)日：2010-04-13

申请号：US10608040

申请日：2003-06-30

申请人： Hajime Ogawa ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

发明人： Hajime Ogawa ,  Taketo Heishi ,  Toshiyuki Sakata ,  Shuichi Takayama ,  Shohei Michimoto ,  Tomoo Hamada ,  Ryoko Miyachi

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F8/443

摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.

摘要翻译： 编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元， 根据来自分析单元等的指令等，执行由用户选择和编译指定的单独优化处理的“if”转换单元和一对指令生成单元）。全局区域分配单元执行优化处理 指定要分配给全球区域的变量的最大数据大小，指定要分配给全局区域的变量，以及关于指定未分配给全局区域的变量的选项和编译指示。

公开(公告)号：US07827542B2

公开(公告)日：2010-11-02

申请号：US11534719

申请日：2006-09-25

申请人： Hajime Ogawa ,  Ryoko Miyachi ,  Toshiyuki Sakata

发明人： Hajime Ogawa ,  Ryoko Miyachi ,  Toshiyuki Sakata

IPC分类号： G06F9/45

CPC分类号： G06F8/445

摘要： A compiler apparatus that improves the performance of loop processing. The compiler apparatus translates a C program that includes a loop into a machine language program, and includes: a movement judgment unit that judges whether or not an instruction which is positioned outside of the loop of the C program can be moved into the loop, based on a state of live ranges of variables used in the instruction; a movement execution unit that moves the instruction into the loop in the case where the movement judgment unit judges that the instruction can be moved into the loop, thereby generating an intermediate program; and a translation unit that translates the intermediate program into the machine language program.

摘要翻译： 一种提高循环处理性能的编译器。 编译装置将包括循环的C程序转换为机器语言程序，并且包括：移动判断单元，其基于C程序的循环以外的指令是否可以移动到循环中 在指令中使用的变量的生存范围的状态; 移动执行单元，其在移动判断单元判断该指令可以移动到循环中的情况下将指令移动到循环中，从而生成中间程序; 以及将中间程序转换为机器语言程序的翻译单元。

公开(公告)号：US07350165B2

公开(公告)日：2008-03-25

申请号：US11087752

申请日：2005-03-24

申请人： Ryoko Miyachi ,  Tomoo Hamada ,  Hajime Ogawa ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

发明人： Ryoko Miyachi ,  Tomoo Hamada ,  Hajime Ogawa ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

IPC分类号： G06F17/50

CPC分类号： G06F8/423 ,  G06F17/505

摘要： A compiler apparatus enables description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.

摘要翻译： 编译装置能够描述现有编程语言中的特定硬件模块，尽管在硬件设计中输入编程语言的描述是不可能的。 在头文件24中，定义了难以形容的编程语言中的特定硬件。 并且编译装置包括分析源程序22的语法的解析器单元30，将语法分析的源程序22转换成将中间代码转换为RTL描述的中间代码和代码生成单元36的中间代码转换单元32。 中间代码转换单元32包括检测单元40，其检测来自源程序22中的头文件24中定义的特定硬件;以及替换单元42，用检测单元40中的检测到的特定硬件替换与特定的对应的中间代码 硬件。

公开(公告)号：US20070074196A1

公开(公告)日：2007-03-29

申请号：US11534719

申请日：2006-09-25

申请人： Hajime OGAWA ,  Ryoko MIYACHI ,  Toshiyuki SAKATA

发明人： Hajime OGAWA ,  Ryoko MIYACHI ,  Toshiyuki SAKATA

IPC分类号： G06F9/45

CPC分类号： G06F8/445

摘要： A compiler apparatus that improves the performance of loop processing. The compiler apparatus translates a C program that includes a loop into a machine language program, and includes: a movement judgment unit that judges whether or not an instruction which is positioned outside of the loop of the C program can be moved into the loop, based on a state of live ranges of variables used in the instruction; a movement execution unit that moves the instruction into the loop in the case where the movement judgment unit judges that the instruction can be moved into the loop, thereby generating an intermediate program; and a translation unit that translates the intermediate program into the machine language program.

摘要翻译： 一种提高循环处理性能的编译器。 编译装置将包括循环的C程序转换为机器语言程序，并且包括：移动判断单元，其基于C程序的循环以外的指令是否可以移动到循环中 在指令中使用的变量的生存范围的状态; 移动执行单元，其在移动判断单元判断该指令可以移动到循环中的情况下将指令移动到循环中，从而生成中间程序; 以及将中间程序转换为机器语言程序的翻译单元。

公开(公告)号：US07171186B2

公开(公告)日：2007-01-30

申请号：US10617773

申请日：2003-07-14

申请人： Ryoko Miyachi ,  Tsutomu Mikami

发明人： Ryoko Miyachi ,  Tsutomu Mikami

IPC分类号： H04B1/16

CPC分类号： H04M1/72519 ,  G01R31/3648 ,  H04M2250/12 ,  H04W52/0261 ,  Y02D70/00

摘要： Data which indicates remaining capacity of a battery in terms of the terminal voltage of the battery is updated by a control unit when necessary, whereby available capacity of the battery is accurately calculated regardless of the extent of deterioration of the battery. In addition to the battery's calculated available capacity, a radio-wave receiving condition and a temperature detected by a temperature detection unit are also taken into consideration to accurately calculate and display an available time. Moreover, the control unit performs the entire process of backing up user data into a non-volatile internal memory (flash memory), which reduces power consumption required for the backup process, resulting in a longer available time.

摘要翻译： 根据需要，通过控制单元来更新指示电池的电池的剩余容量的数据，由此，无论电池的劣化程度如何，都能够准确地计算电池的可用容量。 除了电池的计算可用容量之外，还考虑无线电波接收条件和由温度检测单元检测到的温度以精确地计算和显示可用时间。 此外，控制单元执行将用户数据备份到非易失性内部存储器（闪存）的整个过程，这降低了备份过程所需的功耗，导致更长的可用时间。

公开(公告)号：US20060150135A1

公开(公告)日：2006-07-06

申请号：US11290806

申请日：2005-12-01

申请人： Tomoo Hamada ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

发明人： Tomoo Hamada ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shohei Michimoto ,  Yasuhiro Yamamoto ,  Teruo Kawabata ,  Hirotetsu Tomita

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Provided is an apparatus for generating circuit design information automatically clock gated, for the purpose of alleviating the burden of a designer in performing clock gating to a circuit. The apparatus having an obtaining unit operable to obtain functional structure information and execution sequence information from outside, the functional structure information defining a structure of a function and the execution sequence information defining an execution sequence of the function; a structure information generating unit operable to generate, according to the execution sequence information and the functional structure information, circuit structure information in register transfer level which defines a plurality of circuits that execute the function according to the execution sequence; a gated clock information generating unit operable to generate, according to the execution sequence information and the functional structure information, gated clock information in register transfer level which defines a clock control circuit that supplies, to each of at least one of the circuits, a gated clock that is set to halt clock input when the clock input is unnecessary; and an outputting unit operable to output the gated clock information together with the circuit structure information.

摘要翻译： 提供了一种用于自动生成电路设计信息时钟门控的装置，用于减轻设计者对电路执行时钟门控的负担。 该装置具有可从外部获取功能结构信息和执行序列信息的获取单元，定义功能结构的功能结构信息和定义功能的执行顺序的执行顺序信息; 结构信息生成单元，用于根据执行顺序信息和功能结构信息生成根据执行顺序定义执行功能的多个电路的寄存器传送等级的电路结构信息; 门控时钟信息生成单元，其可操作以根据执行顺序信息和功能结构信息生成寄存器传送级别中的门控时钟信息，其定义时钟控制电路，该时钟控制电路向至少一个电路中的每一个提供门控 当不需要时钟输入时，设置为暂停时钟输入的时钟; 以及输出单元，用于将门控时钟信息与电路结构信息一起输出。

公开(公告)号：US20060107267A1

公开(公告)日：2006-05-18

申请号：US11270515

申请日：2005-11-10

申请人： Ryoko Miyachi ,  Hajime Ogawa ,  Tomoo Hamada ,  Teruo Kawabata

发明人： Ryoko Miyachi ,  Hajime Ogawa ,  Tomoo Hamada ,  Teruo Kawabata

IPC分类号： G06F9/46

CPC分类号： G06F17/505

摘要： An instruction scheduling method according to the present invention allocates each instruction included in an instruction sequence to be synthesized as a circuit to one of execution cycles in the circuit, and includes: detecting a freedom of each instruction, the freedom representing a time period within which the instruction can be allocated; calculating a load of a processing element corresponding to the instruction for each of the execution cycles; and allocating the instructions using the same processing element within the freedoms to different execution cycles based on the load.

摘要翻译： 根据本发明的指令调度方法将要合成的指令序列中包括的每个指令分配给电路中的一个执行周期，并且包括：检测每个指令的自由度，表示其中的自由度，其中 该指令可以分配; 计算与每个执行周期的指令相对应的处理元件的负载; 以及基于所述负载，在所述自由度内使用相同处理元件将指令分配给不同的执行周期。