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    Accessible network of performance index tables
    5.
    发明授权
    Accessible network of performance index tables 失效
    性能指标表可访问网络

    公开(公告)号：US06519640B2

    公开(公告)日：2003-02-11

    申请号：US10082185

    申请日：2002-02-26

    申请人： Ryuichi Hattori ,  Toshihiko Ogura ,  Takashi Oeda ,  Koichi Okazawa ,  Hideki Osaka ,  Tsunehiro Tobita ,  Tsutomu Hara

    发明人： Ryuichi Hattori ,  Toshihiko Ogura ,  Takashi Oeda ,  Koichi Okazawa ,  Hideki Osaka ,  Tsunehiro Tobita ,  Tsutomu Hara

    IPC分类号： G06F1516

    CPC分类号： G06F9/5055 ,  G06F9/5044 ,  G06F2209/5015 ,  H04L29/12047 ,  H04L41/5009 ,  H04L61/15 ,  H04L67/36

    摘要： In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

    摘要翻译： 在通过网络彼此连接的每个信息处理设备中，布置了其功能和性能被注册到其中的服务质量（QOS）表。 当信息处理设备另外与网络链接时，其QOS表被自动地注册到网络的本地目录，使得代理将QOS表的内容转换成要经由用户界面提供给用户的服务信息 。 由于操作，连接到网络的每个信息处理设备的功能和性能的信息被转换成用户的服务信息。 因此，用户可以更多地直接接收必要的服务。

    Information processing system, bus arbiter, and bus controlling method
    10.
    发明授权
    Information processing system, bus arbiter, and bus controlling method 有权
    信息处理系统，总线仲裁器和总线控制方法

    公开(公告)号：US06425037B1

    公开(公告)日：2002-07-23

    申请号：US09407064

    申请日：1999-09-28

    申请人： Nobukazu Kondo ,  Koichi Okazawa ,  Yukihiro Seki ,  Ryuichi Hattori ,  Masaya Umemura ,  Shigemi Adachi ,  Kouichi Nakai ,  Takashi Moriyama

    发明人： Nobukazu Kondo ,  Koichi Okazawa ,  Yukihiro Seki ,  Ryuichi Hattori ,  Masaya Umemura ,  Shigemi Adachi ,  Kouichi Nakai ,  Takashi Moriyama

    IPC分类号： G06F1300

    CPC分类号： G06F13/364

    摘要： The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. The present invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion means for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage means for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request when it performs an access operation, the bus arbiter refers to the access destination information and the data storage status of the storage means and decides whether or not to give a bus occupation right to the bus master.

    摘要翻译： 本发明提供了一种用于防止诸如通过具有低速IO接入的总线竞争阻塞的主存储访问的事务的执行并提高总线占用效率的手段。本发明包括第一总线，第二总线，多个 连接到两个总线的模块，用于在两个总线之间执行信息的协议转换的总线转换装置，用于仲裁总线主机的总线占用权请求的总线仲裁器，以及用于当存储访问数据达到预定量时存储访问数据的存储装置 访问目的地是预定模块。 每个总线主机输出接入目的地信息，当总线仲裁器在执行访问操作时判断其中一个总线主机发出总线占用权请求时，总线仲裁器参考存取装置的访问目的地信息和数据存储状态 并决定是否给予巴士总线职业权。